332dab6878
target/riscv: setup everything for rv64 to support rv128 execution
...
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
2b5470843a
target/riscv: array for the 64 upper bits of 128-bit registers
...
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr >
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:10 +10:00
dfdb46a376
target/riscv: Fix position of 'experimental' comment
...
When commit 0643c12e4b0643c12e4bphilipp.tomsich@vrull.eu >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20220106134020.1628889-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-01-08 15:46:09 +10:00
07cb270a9a
target/riscv: Enable the Hypervisor extension by default
...
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com >
2022-01-08 15:46:09 +10:00
6ca7155a8c
target/riscv: Mark the Hypervisor extension as non experimental
...
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20220105213937.1113508-6-alistair.francis@opensource.wdc.com >
2022-01-08 15:46:09 +10:00
0643c12e4b
target/riscv: Enable bitmanip Zb[abcs] instructions
...
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
719d3561b2
target/riscv: gdb: support vector registers for rv64 & rv32
...
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com >
Signed-off-by: Greentime Hu <greentime.hu@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
9ec6622db3
target/riscv: drop vector 0.7.1 and add 1.0 support
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20211210075704.23951-2-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
e523773040
target/riscv: zfh: add Zfhmin cpu property
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
13fb8c7b42
target/riscv: zfh: add Zfh cpu property
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
263e2ab20c
target/riscv: Make riscv_cpu_tlb_fill sysemu only
...
The fallback code in cpu_loop_exit_sigsegv is sufficient
for riscv linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Warner Losh <imp@bsdimp.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-11-02 07:00:52 -04:00
0ee9a4e57e
target/riscv: Allow experimental J-ext to be turned on
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
bd5594ca28
target/riscv: Print new PM CSRs in QEMU logs
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
4bbe8033fc
target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
...
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-28 14:39:23 +10:00
665b90d8a4
target/riscv: Use riscv_csrrw_debug for cpu_dump
...
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 23:35:47 +10:00
92371bd903
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
...
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
db23e5d981
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
...
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
e91a7227cb
target/riscv: Split misa.mxl and misa.ext
...
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
9d3d60b704
target/riscv: Organise the CPU properties
...
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
2021-10-22 07:47:51 +10:00
e573a7f325
target/riscv: line up all of the registers in the info register dump
...
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-22 07:47:51 +10:00
9916ea3c97
target/riscv: Remove RVB (replaced by Zb[abcs])
...
With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.
Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
https://lists.riscv.org/g/tech-bitmanip/message/532
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:41:33 +10:00
878dd0e9ac
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
...
The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension. The first
new instructions through the door (these have completed public review)
are Zb[abcs].
This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-10-07 08:32:55 +10:00
0f0b70eeec
target/riscv: Expose interrupt pending bits as GPIO lines
...
Expose the 12 interrupt pending bits in MIP as GPIO lines.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Tested-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
a44da25aa6
target/riscv: Update the ePMP CSR address
...
Update the ePMP CSRs to match the 0.9.3 ePMP spec
https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com
2021-09-21 07:56:49 +10:00
17b3c353e6
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
...
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Warner Losh <imp@bsdimp.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-Id: <20210911165434.531552-19-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-09-14 12:00:21 -07:00
a8b37120d4
target/riscv: Don't wrongly override isa version
...
For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-09-01 11:59:12 +10:00
d2c1a177b1
target/riscv: rvb: add b-ext version cpu option
...
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:46 +10:00
d52e94081e
target/riscv: rvb: support and turn on B-extension from command line
...
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:46 +10:00
a722701dd3
target/riscv: Dump CSR mscratch/sscratch/satp
...
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
9a575d33fb
target/riscv: Remove unnecessary riscv_*_names[] declaration
...
riscv_excp_names[] and riscv_intr_names[] are only referenced by
target/riscv/cpu.c locally.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-06-08 09:59:43 +10:00
119065574d
hw/core: Constify TCGCPUOps
...
We no longer have any runtime modifications to this struct,
so declare them all const.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
08928c6d0d
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
...
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org >
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
715e3c1afb
cpu: Move CPUClass::write_elf* to SysemuCPUOps
...
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-19-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
feece4d070
cpu: Move CPUClass::vmsd to SysemuCPUOps
...
Migration is specific to system emulation.
- Move the CPUClass::vmsd field to SysemuCPUOps,
- restrict VMSTATE_CPU() macro to sysemu,
- vmstate_dummy is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-16-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
8b80bd28a5
cpu: Introduce SysemuCPUOps structure
...
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org >
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
744c72a837
cpu: Rename CPUClass vmsd -> legacy_vmsd
...
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3ddhttps://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Cc: Peter Maydell <peter.maydell@linaro.org >
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-05-26 15:33:59 -07:00
3820602f80
target/riscv: Remove the hardcoded RVXLEN macro
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
2021-05-11 20:02:07 +10:00
6cfcf77573
target/riscv: fix a typo with interrupt names
...
Interrupt names have been swapped in 205377f8emmanuel.blot@sifive.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:02:07 +10:00
ed6eebaaaf
target/riscv: Add ePMP support for the Ibex CPU
...
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
5da9514e96
target/riscv: Add a config option for ePMP
...
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com >
Signed-off-by: Hou Weiying <weiying_hou@outlook.com >
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
2021-05-11 20:02:06 +10:00
330d2ae32a
target/riscv: Convert the RISC-V exceptions to an enum
...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
2021-05-11 20:02:06 +10:00
6ddc7069f5
target/riscv: Add Shakti C class CPU
...
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
01e723bf18
target/riscv: Align the data type of reset vector address
...
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong <dylan@andestech.com >
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com >
Reviewed-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210329034801.22667-1-dylan@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
ac12b60103
target/riscv: Remove privilege v1.9 specific CSR related code
...
Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.
Signed-off-by: Atish Patra <atish.patra@wdc.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com >
[Changes by AF:
- Rebase on latest patches
- Bump the vmstate_riscv_cpu version_id and minimum_version_id
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-05-11 20:01:10 +10:00
ec352d0cab
target/riscv: Add proper two-stage lookup exception detection
...
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.
What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-22 21:54:40 -04:00
cba42d61a3
Various spelling fixes
...
An assorted set of spelling fixes in various places.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru >
Reviewed-by: Stefan Weil <sw@weilnetz.de >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Peter Maydell <peter.maydell@linaro.org >
Message-Id: <20210309111510.79495-1-mjt@msgid.tls.msk.ru >
Signed-off-by: Laurent Vivier <laurent@vivier.eu >
2021-03-09 21:19:10 +01:00
43a9658889
target-riscv: support QMP dump-guest-memory
...
Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.
Now ELF notes of RISC-V only contain prstatus elf notes.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Mingwang Li <limingwang@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Andrew Jones <drjones@redhat.com >
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com >
Message-id: 20210201124458.1248-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-03-04 09:43:29 -05:00
7827168471
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
...
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Message-Id: <20210204163931.7358-16-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:15 -10:00
8535dd702d
cpu: move do_unaligned_access to tcg_ops
...
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
[claudio: make the field presence in cpu.h unconditional, removing the ifdefs]
Message-Id: <20210204163931.7358-12-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
cbc183d2d9
cpu: move cc->transaction_failed to tcg_ops
...
Signed-off-by: Claudio Fontana <cfontana@suse.de >
Reviewed-by: Alex Bennée <alex.bennee@linaro.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
avoiding its use in headers used by common_ss code (should be poisoned).
Note: need to be careful with the use of CONFIG_USER_ONLY,
Message-Id: <20210204163931.7358-11-cfontana@suse.de >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2021-02-05 10:24:14 -10:00
Frédéric Pétrot
Philipp Tomsich
Alistair Francis
Vineet Gupta
Hsiangkai Wang
Frank Chang
Richard Henderson
Alexey Baturo
Travis Geiselbrecht
Philippe Mathieu-Daudé
LIU Zhiwei
Kito Cheng
Changbin Du
Bin Meng
Emmanuel Blot
Hou Weiying
Vijai Kumar K
Dylan Jhong
Atish Patra
Georg Kotheimer
Michael Tokarev
Yifei Jiang
Claudio Fontana