diff --git a/hw/display/esp_rgb.c b/hw/display/esp_rgb.c
index 68654e3dcb..345ef37d39 100644
--- a/hw/display/esp_rgb.c
+++ b/hw/display/esp_rgb.c
@@ -307,9 +307,9 @@ static void esp_rgb_init(Object *obj)
 }
 
 
-static void esp_rgb_reset(DeviceState *dev)
+static void esp_rgb_reset_hold(Object *obj, ResetType type)
 {
-    ESPRgbState* s = ESP_RGB(dev);
+    ESPRgbState* s = ESP_RGB(obj);
 
     /* Default window size */
     s->width = ESP_RGB_MAX_WIDTH;
@@ -325,8 +325,9 @@ static void esp_rgb_reset(DeviceState *dev)
 static void esp_rgb_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp_rgb_reset;
+    rc->phases.hold = esp_rgb_reset_hold;
     dc->realize = esp_rgb_realize;
 }
 
diff --git a/hw/dma/esp_gdma.c b/hw/dma/esp_gdma.c
index 4f8d8aa399..565367e43c 100644
--- a/hw/dma/esp_gdma.c
+++ b/hw/dma/esp_gdma.c
@@ -555,10 +555,10 @@ static void esp_gdma_check_and_start_mem_transfer(ESPGdmaState *s, uint32_t chan
         state_out->link &= R_GDMA_OUT_LINK_ADDR_MASK;
         state_in->link  &= R_GDMA_IN_LINK_ADDR_MASK;
         /* Same goes for the status */
-        esp_gdma_clear_status(&state_in->int_state, 
+        esp_gdma_clear_status(&state_in->int_state,
                               R_GDMA_INTERRUPT_IN_DONE_MASK  |
                               R_GDMA_INTERRUPT_IN_SUC_EOF_MASK);
-        esp_gdma_clear_status(&state_out->int_state, 
+        esp_gdma_clear_status(&state_out->int_state,
                               R_GDMA_INTERRUPT_OUT_DONE_MASK |
                               R_GDMA_INTERRUPT_OUT_EOF_MASK  );
 
@@ -749,10 +749,10 @@ static void esp_gdma_check_and_start_mem_transfer(ESPGdmaState *s, uint32_t chan
             state_in->suc_eof_desc_addr = in_addr;
 
             /* Set the transfer as completed for both the IN and OUT link */
-            esp_gdma_set_status(&state_in->int_state, 
+            esp_gdma_set_status(&state_in->int_state,
                                 R_GDMA_INTERRUPT_IN_DONE_MASK  |
                                 R_GDMA_INTERRUPT_IN_SUC_EOF_MASK);
-            esp_gdma_set_status(&state_out->int_state, 
+            esp_gdma_set_status(&state_out->int_state,
                                 R_GDMA_INTERRUPT_OUT_DONE_MASK |
                                 R_GDMA_INTERRUPT_OUT_EOF_MASK);
         }
@@ -936,10 +936,10 @@ static Property esp_gdma_properties[] = {
 };
 
 
-static void esp_gdma_reset(DeviceState *dev)
+static void esp_gdma_reset_hold(Object *obj, ResetType type)
 {
-    ESPGdmaState *s = ESP_GDMA(dev);
-    ESPGdmaClass *klass = ESP_GDMA_GET_CLASS(dev);
+    ESPGdmaState *s = ESP_GDMA(obj);
+    ESPGdmaClass *klass = ESP_GDMA_GET_CLASS(obj);
 
     for (int dir = 0; dir < ESP_GDMA_CONF_COUNT; dir++) {
         for (int chan = 0; chan < klass->m_channel_count; chan++) {
@@ -973,7 +973,7 @@ static void esp_gdma_init(Object *obj)
 {
     ESPGdmaState *s = ESP_GDMA(obj);
     ESPGdmaClass *klass = ESP_GDMA_GET_CLASS(obj);
-    
+
     /* Make sure the number of channels passed by the child class is correct, use an abitrary limit */
     if (klass->m_channel_count == 0 || klass->m_channel_count > 16) {
         error_report("[GDMA] %s: invalid number of DMA channels (%zu)", __func__, klass->m_channel_count);
@@ -992,15 +992,16 @@ static void esp_gdma_init(Object *obj)
         }
     }
 
-    esp_gdma_reset((DeviceState*) s);
+    esp_gdma_reset_hold(obj, RESET_TYPE_COLD);
 }
 
 
 static void esp_gdma_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp_gdma_reset;
+    rc->phases.hold = esp_gdma_reset_hold;
     dc->realize = esp_gdma_realize;
     device_class_set_props(dc, esp_gdma_properties);
 }
diff --git a/hw/misc/esp32c3_cache.c b/hw/misc/esp32c3_cache.c
index 831dc0bd0a..1879b5c2df 100644
--- a/hw/misc/esp32c3_cache.c
+++ b/hw/misc/esp32c3_cache.c
@@ -204,9 +204,9 @@ static const MemoryRegionOps esp32c3_cache_mem_ops = {
     .valid.accepts = esp32c3_cache_mem_accepts,
 };
 
-static void esp32c3_cache_reset(DeviceState *dev)
+static void esp32c3_cache_reset_hold(Object *obj, ResetType type)
 {
-    ESP32C3CacheState *s = ESP32C3_CACHE(dev);
+    ESP32C3CacheState *s = ESP32C3_CACHE(obj);
     memset(s->regs, 0, ESP32C3_CACHE_REG_COUNT * sizeof(*s->regs));
 
     /* Initialize the MMU with invalid entries */
@@ -223,7 +223,7 @@ static void esp32c3_cache_reset(DeviceState *dev)
 static void esp32c3_cache_realize(DeviceState *dev, Error **errp)
 {
     /* Initialize the registers */
-    esp32c3_cache_reset(dev);
+    esp32c3_cache_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
 
     ESP32C3CacheState *s = ESP32C3_CACHE(dev);
 
@@ -263,8 +263,9 @@ static Property esp32c3_cache_properties[] = {
 static void esp32c3_cache_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_cache_reset;
+    rc->phases.hold = esp32c3_cache_reset_hold;
     dc->realize = esp32c3_cache_realize;
     device_class_set_props(dc, esp32c3_cache_properties);
 }
diff --git a/hw/misc/esp32c3_jtag.c b/hw/misc/esp32c3_jtag.c
index 58838d9801..82ee69717b 100644
--- a/hw/misc/esp32c3_jtag.c
+++ b/hw/misc/esp32c3_jtag.c
@@ -35,9 +35,10 @@ static const MemoryRegionOps esp32c3_jtag_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32c3_jtag_reset(DeviceState *dev)
+static void esp32c3_jtag_reset_hold(Object *obj, ResetType type)
 {
-    (void) dev;
+    (void) obj;
+    (void) type;
 }
 
 static void esp32c3_jtag_realize(DeviceState *dev, Error **errp)
@@ -59,8 +60,9 @@ static void esp32c3_jtag_init(Object *obj)
 static void esp32c3_jtag_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_jtag_reset;
+    rc->phases.hold = esp32c3_jtag_reset_hold;
     dc->realize = esp32c3_jtag_realize;
 }
 
diff --git a/hw/misc/esp32c3_rtc_cntl.c b/hw/misc/esp32c3_rtc_cntl.c
index c068d5a14c..14c045c901 100644
--- a/hw/misc/esp32c3_rtc_cntl.c
+++ b/hw/misc/esp32c3_rtc_cntl.c
@@ -123,10 +123,10 @@ static const MemoryRegionOps esp_rtc_cntl_ops = {
 };
 
 
-static void esp32c3_rtc_cntl_reset(DeviceState *dev)
+static void esp32c3_rtc_cntl_reset_hold(Object *obj, ResetType type)
 {
     static bool first_boot = true;
-    ESP32C3RtcCntlState *s = ESP32C3_RTC_CNTL(dev);
+    ESP32C3RtcCntlState *s = ESP32C3_RTC_CNTL(obj);
     s->options0 = 0;
 
     if (first_boot) {
@@ -141,7 +141,7 @@ static void esp32c3_rtc_cntl_reset(DeviceState *dev)
 static void esp32c3_rtc_cntl_realize(DeviceState *dev, Error **errp)
 {
     ESP32C3RtcCntlState *s = ESP32C3_RTC_CNTL(dev);
-    esp32c3_rtc_cntl_reset(dev);
+    esp32c3_rtc_cntl_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
     (void) s;
 }
 
@@ -165,8 +165,9 @@ static void esp32c3_rtc_cntl_init(Object *obj)
 static void esp32c3_rtc_cntl_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_rtc_cntl_reset;
+    rc->phases.hold = esp32c3_rtc_cntl_reset_hold;
     dc->realize = esp32c3_rtc_cntl_realize;
 }
 
diff --git a/hw/misc/esp32c3_xts_aes.c b/hw/misc/esp32c3_xts_aes.c
index 04a13dd17a..41c44673cc 100644
--- a/hw/misc/esp32c3_xts_aes.c
+++ b/hw/misc/esp32c3_xts_aes.c
@@ -302,9 +302,9 @@ static const MemoryRegionOps esp32c3_xts_aes_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32c3_xts_aes_reset(DeviceState *dev)
+static void esp32c3_xts_aes_reset_hold(Object *obj, ResetType type)
 {
-    ESP32C3XtsAesState *s = ESP32C3_XTS_AES(dev);
+    ESP32C3XtsAesState *s = ESP32C3_XTS_AES(obj);
     memset(s->plaintext, 0, ESP32C3_XTS_AES_PLAIN_REG_CNT * sizeof(uint32_t));
     memset(s->ciphertext, 0, ESP32C3_XTS_AES_PLAIN_REG_CNT * sizeof(uint32_t));
     s->state = XTS_AES_IDLE;
@@ -342,9 +342,10 @@ static void esp32c3_xts_aes_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     ESP32C3XtsAesClass* esp32c3_xts_aes = ESP32C3_XTS_AES_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
     dc->realize = esp32c3_xts_aes_realize;
-    dc->legacy_reset = esp32c3_xts_aes_reset;
+    rc->phases.hold = esp32c3_xts_aes_reset_hold;
 
     esp32c3_xts_aes->is_ciphertext_spi_visible = esp32c3_xts_aes_is_ciphertext_spi_visible;
     esp32c3_xts_aes->is_flash_enc_enabled = esp32c3_xts_aes_is_flash_enc_enabled;
diff --git a/hw/nvram/esp_efuse.c b/hw/nvram/esp_efuse.c
index c4b7c494b6..7ee3fd64ce 100644
--- a/hw/nvram/esp_efuse.c
+++ b/hw/nvram/esp_efuse.c
@@ -569,9 +569,9 @@ static const MemoryRegionOps esp_efuse_ops = {
 };
 
 
-static void esp_efuse_reset(DeviceState *dev)
+static void esp_efuse_reset_hold(Object *obj, ResetType type)
 {
-    ESPEfuseState *s = ESP_EFUSE(dev);
+    ESPEfuseState *s = ESP_EFUSE(obj);
     timer_del(&s->op_timer);
     qemu_irq_lower(s->irq);
     esp_efuse_reload_from_blk(s);
@@ -606,7 +606,7 @@ static void esp_efuse_realize(DeviceState *dev, Error **errp)
             goto error;
         }
 
-        esp_efuse_reset((DeviceState*) s);
+        esp_efuse_reset_hold(OBJECT(s), RESET_TYPE_COLD);
     }
 
     /* State machine is ready */
@@ -639,8 +639,9 @@ static void esp_efuse_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     ESPEfuseClass* esp_efuse = ESP_EFUSE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp_efuse_reset;
+    rc->phases.hold = esp_efuse_reset_hold;
     dc->realize = esp_efuse_realize;
     device_class_set_props(dc, esp_efuse_properties);
 
diff --git a/hw/riscv/esp32c3_clk.c b/hw/riscv/esp32c3_clk.c
index 8f29c57fcf..10aa7f412c 100644
--- a/hw/riscv/esp32c3_clk.c
+++ b/hw/riscv/esp32c3_clk.c
@@ -106,9 +106,9 @@ static const MemoryRegionOps esp32c3_clock_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32c3_clock_reset(DeviceState *dev)
+static void esp32c3_clock_reset_hold(Object *obj, ResetType type)
 {
-    ESP32C3ClockState *s = ESP32C3_CLOCK(dev);
+    ESP32C3ClockState *s = ESP32C3_CLOCK(obj);
     /* On board reset, set the proper clocks and dividers */
     s->sysclk = ( 1 << R_SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_SHIFT) |
                 (ESP32C3_CLK_SEL_PLL << R_SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_SHIFT) |
@@ -129,7 +129,7 @@ static void esp32c3_clock_reset(DeviceState *dev)
 static void esp32c3_clock_realize(DeviceState *dev, Error **errp)
 {
     /* Initialize the registers */
-    esp32c3_clock_reset(dev);
+    esp32c3_clock_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
 }
 
 static void esp32c3_clock_init(Object *obj)
@@ -151,8 +151,9 @@ static void esp32c3_clock_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     ESP32C3ClockClass* esp32c3_clock = ESP32C3_CLOCK_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_clock_reset;
+    rc->phases.hold = esp32c3_clock_reset_hold;
     dc->realize = esp32c3_clock_realize;
 
     esp32c3_clock->get_ext_dev_enc_dec_ctrl = esp32c3_clock_get_ext_dev_enc_dec_ctrl;
diff --git a/hw/riscv/esp32c3_intmatrix.c b/hw/riscv/esp32c3_intmatrix.c
index ab0f3f0115..17d99bf573 100644
--- a/hw/riscv/esp32c3_intmatrix.c
+++ b/hw/riscv/esp32c3_intmatrix.c
@@ -343,9 +343,9 @@ static const MemoryRegionOps esp_intmatrix_ops = {
 };
 
 
-static void esp32c3_intmatrix_reset(DeviceState *dev)
+static void esp32c3_intmatrix_reset_hold(Object *obj, ResetType type)
 {
-    ESP32C3IntMatrixState *s = ESP32C3_INTMATRIX(dev);
+    ESP32C3IntMatrixState *s = ESP32C3_INTMATRIX(obj);
     RISCVCPU *cpu = &s->cpu->parent_obj;
 
     memset(s->irq_map, 0, sizeof(s->irq_map));
@@ -370,7 +370,7 @@ static void esp32c3_intmatrix_realize(DeviceState *dev, Error **errp)
     EspRISCVCPU *cpu = s->cpu;
     EspRISCVCPUClass *cpu_klass = ESP_CPU_GET_CLASS(cpu);
 
-    esp32c3_intmatrix_reset(dev);
+    esp32c3_intmatrix_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
 
     /* Register MIE callback */
     assert(cpu);
@@ -401,8 +401,9 @@ static Property esp32c3_intmatrix_properties[] = {
 static void esp32c3_intmatrix_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_intmatrix_reset;
+    rc->phases.hold = esp32c3_intmatrix_reset_hold;
     dc->realize = esp32c3_intmatrix_realize;
     device_class_set_props(dc, esp32c3_intmatrix_properties);
 }
diff --git a/hw/ssi/esp32c3_spi.c b/hw/ssi/esp32c3_spi.c
index 8639783743..e8bd33aad0 100644
--- a/hw/ssi/esp32c3_spi.c
+++ b/hw/ssi/esp32c3_spi.c
@@ -406,9 +406,9 @@ static const MemoryRegionOps esp32c3_spi_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32c3_spi_reset(DeviceState *dev)
+static void esp32c3_spi_reset_hold(Object *obj, ResetType type)
 {
-    ESP32C3SpiState *s = ESP32C3_SPI(dev);
+    ESP32C3SpiState *s = ESP32C3_SPI(obj);
     memset(s->data_reg, 0, ESP32C3_SPI_BUF_WORDS * sizeof(uint32_t));
     s->mem_ctrl1 = FIELD_DP32(s->mem_ctrl1, SPI_MEM_CTRL1, CS_HOLD_DLY_RES, 0x3ff);
     s->mem_clock = FIELD_DP32(s->mem_clock, SPI_MEM_CLOCK, CLKCNT_N, 3);
@@ -447,7 +447,7 @@ static void esp32c3_spi_init(Object *obj)
     sysbus_init_mmio(sbd, &s->iomem);
     // sysbus_init_irq(sbd, &s->irq);
 
-    esp32c3_spi_reset(DEVICE(s));
+    esp32c3_spi_reset_hold(obj, RESET_TYPE_COLD);
 
     s->spi = ssi_create_bus(DEVICE(s), "spi");
     qdev_init_gpio_out_named(DEVICE(s), &s->cs_gpio[0], SSI_GPIO_CS, ESP32C3_SPI_CS_COUNT);
@@ -460,8 +460,9 @@ static Property esp32c3_spi_properties[] = {
 static void esp32c3_spi_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_spi_reset;
+    rc->phases.hold = esp32c3_spi_reset_hold;
     dc->realize = esp32c3_spi_realize;
     device_class_set_props(dc, esp32c3_spi_properties);
 }
diff --git a/hw/timer/esp32c3_timg.c b/hw/timer/esp32c3_timg.c
index 77a82f643d..724a2116cf 100644
--- a/hw/timer/esp32c3_timg.c
+++ b/hw/timer/esp32c3_timg.c
@@ -666,9 +666,9 @@ static const MemoryRegionOps esp32c3_timg_ops = {
 };
 
 
-static void esp32c3_timg_reset(DeviceState* ts)
+static void esp32c3_timg_reset_hold(Object *obj, ResetType type)
 {
-    ESP32C3TimgState *s = ESP32C3_TIMG(ts);
+    ESP32C3TimgState *s = ESP32C3_TIMG(obj);
 
     /* Reset watchdog */
     esp32c3_virtual_counter_reset(&s->wdt.counter);
@@ -724,7 +724,7 @@ static void esp32c3_timg_init(Object *obj)
     timer_init_ns(esp32c3_virtual_counter_get_timer(&s->t0.counter), QEMU_CLOCK_VIRTUAL, esp32c3_t0_cb, &s->t0);
 
     /* Set the initial values for the internal fields */
-    esp32c3_timg_reset((DeviceState*) s);
+    esp32c3_timg_reset_hold(obj, RESET_TYPE_COLD);
 }
 
 static Property esp32c3_timg_properties[] = {
@@ -735,8 +735,9 @@ static Property esp32c3_timg_properties[] = {
 static void esp32c3_timg_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32c3_timg_reset;
+    rc->phases.hold = esp32c3_timg_reset_hold;
     dc->realize = esp32c3_timg_realize;
     device_class_set_props(dc, esp32c3_timg_properties);
 }
diff --git a/hw/timer/esp_systimer.c b/hw/timer/esp_systimer.c
index 3daff32dc9..75f9861bd7 100644
--- a/hw/timer/esp_systimer.c
+++ b/hw/timer/esp_systimer.c
@@ -573,9 +573,9 @@ static void esp_systimer_default_conf(ESPSysTimerState *s)
 }
 
 
-static void esp_systimer_reset(DeviceState* ts)
+static void esp_systimer_reset_hold(Object *obj, ResetType type)
 {
-    ESPSysTimerState *s = ESP_SYSTIMER(ts);
+    ESPSysTimerState *s = ESP_SYSTIMER(obj);
     for (int i = 0; i < ESP_SYSTIMER_COMP_COUNT; i++) {
         ESPSysTimerComp* comp = &s->comparators[i];
         QEMUTimer qtimer = comp->qtimer;
@@ -625,8 +625,9 @@ static void esp_systimer_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     ESPSysTimerClass *class = ESP_SYSTIMER_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp_systimer_reset;
+    rc->phases.hold = esp_systimer_reset_hold;
     dc->realize = esp_systimer_realize;
 
     class->comparators_reprogram = esp_systimer_comparator_reprogram_all;