hw/net/can: remove interrupt handling from ESP32 TWAI state
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+2
-24
@@ -36,8 +36,6 @@ static const VMStateDescription vmstate_esp32_twai = {
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.minimum_version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT(sja_state, Esp32TWAIState, 0, vmstate_can_sja, CanSJA1000State),
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VMSTATE_STRUCT(sja_state, Esp32TWAIState, 0, vmstate_can_sja, CanSJA1000State),
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VMSTATE_UINT32(interrupt_enable, Esp32TWAIState),
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VMSTATE_UINT32(interrupt_state, Esp32TWAIState),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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}
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}
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};
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};
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@@ -49,34 +47,14 @@ static void esp32_twai_reset(Object *obj, ResetType type)
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/* Reset underlying SJA1000 hardware to its default state */
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/* Reset underlying SJA1000 hardware to its default state */
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can_sja_hardware_reset(&s->sja_state);
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can_sja_hardware_reset(&s->sja_state);
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/* Initialize interrupt control registers to their reset values:
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* - Enable Transmit, Receive and Error interrupts by default
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* - Clear any pending interrupt state
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*/
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s->interrupt_enable = ESP32_TWAI_INTR_TI | ESP32_TWAI_INTR_RI |
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ESP32_TWAI_INTR_EI;
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s->interrupt_state = 0;
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}
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}
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/* Interrupt handler for SJA1000 events */
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/* Interrupt handler for SJA1000 events */
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static void esp32_twai_irq_handler(void *opaque, int irq_num, int level)
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static void esp32_twai_irq_handler(void *opaque, int irq_num, int level)
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{
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{
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Esp32TWAIState *s = (Esp32TWAIState *)opaque;
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Esp32TWAIState *d = opaque;
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/* Track the interrupt state from the underlying SJA1000 controller */
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qemu_set_irq(d->irq, level);
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s->interrupt_state = level;
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/* Only forward interrupts to the CPU if they are enabled in the mask.
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* The interrupt enable mask defaults to enabled state for basic operation.
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*/
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if (s->interrupt_enable != 0) {
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if (level) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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}
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}
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/* Memory-mapped I/O read handler for the TWAI peripheral.
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/* Memory-mapped I/O read handler for the TWAI peripheral.
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@@ -24,11 +24,6 @@
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/* ESP32 uses 32-bit aligned addresses, so multiply SJA1000 memory size by 4 */
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/* ESP32 uses 32-bit aligned addresses, so multiply SJA1000 memory size by 4 */
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#define ESP32_TWAI_MEM_SIZE (CAN_SJA_MEM_SIZE << 2)
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#define ESP32_TWAI_MEM_SIZE (CAN_SJA_MEM_SIZE << 2)
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/* ESP32 TWAI interrupt definitions */
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#define ESP32_TWAI_INTR_TI (0x1 << 1) /* Transmit Interrupt */
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#define ESP32_TWAI_INTR_RI (0x1 << 0) /* Receive Interrupt */
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#define ESP32_TWAI_INTR_EI (0x1 << 2) /* Error Interrupt */
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typedef struct Esp32TWAIState {
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typedef struct Esp32TWAIState {
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SysBusDevice parent_obj;
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegion iomem;
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@@ -36,8 +31,6 @@ typedef struct Esp32TWAIState {
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CanSJA1000State sja_state; /* Underlying SJA1000 controller state */
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CanSJA1000State sja_state; /* Underlying SJA1000 controller state */
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qemu_irq irq; /* System bus IRQ */
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qemu_irq irq; /* System bus IRQ */
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qemu_irq irq_handler; /* Interrupt proxy handler */
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qemu_irq irq_handler; /* Interrupt proxy handler */
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uint32_t interrupt_enable; /* Interrupt enable mask */
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uint32_t interrupt_state; /* Current interrupt state */
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CanBusState *canbus; /* CAN bus interface */
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CanBusState *canbus; /* CAN bus interface */
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} Esp32TWAIState;
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} Esp32TWAIState;
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