hw/xtensa: add ESP32-S3 core configuration
This commit is contained in:
Dmitry Yakovlev
committed by
Ivan Grokhotkov
Ivan Grokhotkov
parent
dba9c9dfa3
commit
27d3ad1531
@@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#include "core-esp32s3/core-isa.h"
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#include "overlay_tool.h"
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#define xtensa_modules xtensa_modules_esp32s3
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#include "core-esp32s3/xtensa-modules.inc.c"
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extern const XtensaOpcodeTranslators xtensa_tie_opcodes;
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static const XtensaOpcodeTranslators* esp32s3_opcode_translators[] = {
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&xtensa_core_opcodes,
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&xtensa_fpu_opcodes,
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&xtensa_tie_opcodes,
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NULL
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};
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static XtensaConfig xtensa_core_esp32s3 __attribute__((unused)) = {
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.name = "esp32s3",
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.gdb_regmap = {
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.reg = {
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#include "core-esp32s3/gdb-config.inc.c"
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}
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},
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.isa_internal = &xtensa_modules,
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.clock_freq_khz = 40000,
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.opcode_translators = esp32s3_opcode_translators,
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DEFAULT_SECTIONS
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};
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REGISTER_CORE(xtensa_core_esp32s3)
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@@ -0,0 +1,682 @@
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/*
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* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
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* processor CORE configuration
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*
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* See <xtensa/config/core.h>, which includes this file, for more details.
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*/
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/* Xtensa processor core configuration information.
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Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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/*
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* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
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#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
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#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
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#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
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#define XCHAL_MAX_INSTRUCTION_SIZE 4 /* max instr bytes (3..8) */
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#define XCHAL_HAVE_DEBUG 1 /* debug option */
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#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
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#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
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#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
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#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
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#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
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#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
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#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
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#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
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#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
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#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
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#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
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#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
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#define XCHAL_HAVE_L32R 1 /* L32R instruction */
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#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
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#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
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#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
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#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
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#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
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#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
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#define XCHAL_HAVE_ABS 1 /* ABS instruction */
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/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
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/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
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#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
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#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
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#define XCHAL_HAVE_SPECULATION 0 /* speculation */
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#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
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#define XCHAL_NUM_CONTEXTS 1 /* */
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#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
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#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
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#define XCHAL_HAVE_PRID 1 /* processor ID register */
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#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
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#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
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#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
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#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
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#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
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#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
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#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
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#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
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#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
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#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
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#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
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#define XCHAL_HAVE_FUSION 0 /* Fusion*/
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#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
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#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
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#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
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#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
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#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
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#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
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#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
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#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
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#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
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#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
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#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
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#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
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#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
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#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
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#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
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#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
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#define XCHAL_HAVE_HIFI_MINI 0
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#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
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#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
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#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
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#define XCHAL_HAVE_FP 1 /* single prec floating point */
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#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
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#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
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#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
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#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
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#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
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#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
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#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
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#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
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#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
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#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
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#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
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#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
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#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
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#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
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#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
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#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
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#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
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#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
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#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
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#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
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#define XCHAL_HAVE_PDX 0 /* PDX */
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#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
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#define XCHAL_HAVE_PDX4 0 /* PDX4 */
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#define XCHAL_HAVE_PDX8 0 /* PDX8 */
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#define XCHAL_HAVE_PDX16 0 /* PDX16 */
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#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
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#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
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#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
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#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
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#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
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#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
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#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
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#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
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#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
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#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
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#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
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#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
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#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
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#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
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#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
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#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
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#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
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#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
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#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
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#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
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#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
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#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
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#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
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#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
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#define XCHAL_HAVE_VISIONC 0 /* Vision C */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
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#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
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#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
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#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
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#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
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(1 = 5-stage, 2 = 7-stage) */
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#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
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#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
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/* In T1050, applies to selected core load and store instructions (see ISA): */
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#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
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#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
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#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
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#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
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#define XCHAL_SW_VERSION 1200012 /* sw version of this header */
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#define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
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(CoreID) set in the Xtensa
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Processor Generator */
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#define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
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/*
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* These definitions describe the hardware targeted by this software.
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*/
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#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
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#define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
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#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
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#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
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#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
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#define XCHAL_HW_VERSION 270012 /* major*100+minor */
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#define XCHAL_HW_REL_LX7 1
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#define XCHAL_HW_REL_LX7_0 1
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#define XCHAL_HW_REL_LX7_0_12 1
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#define XCHAL_HW_CONFIGID_RELIABLE 1
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/* If software targets a *range* of hardware versions, these are the bounds: */
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#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
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#define XCHAL_HW_MIN_VERSION_MINOR 12 /* minor v of earliest tgt hw */
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#define XCHAL_HW_MIN_VERSION 270012 /* earliest targeted hw */
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#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION_MINOR 12 /* minor v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION 270012 /* latest targeted hw */
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
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#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
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#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
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#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
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#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
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#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
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#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
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#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
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#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
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#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
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#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
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#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
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#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
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#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
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#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
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#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
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#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
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#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
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#define XCHAL_HAVE_AXI 0 /* AXI bus */
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#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
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#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
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#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
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#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
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/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
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/* Number of cache sets in log2(lines per way): */
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#define XCHAL_ICACHE_SETWIDTH 0
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#define XCHAL_DCACHE_SETWIDTH 0
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/* Cache set associativity (number of ways): */
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#define XCHAL_ICACHE_WAYS 1
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#define XCHAL_DCACHE_WAYS 1
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/* Cache features: */
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#define XCHAL_ICACHE_LINE_LOCKABLE 0
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#define XCHAL_DCACHE_LINE_LOCKABLE 0
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#define XCHAL_ICACHE_ECC_PARITY 0
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#define XCHAL_DCACHE_ECC_PARITY 0
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#define XCHAL_ICACHE_ECC_WIDTH 1
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#define XCHAL_DCACHE_ECC_WIDTH 1
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|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 1
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 1
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 67108864 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM0 1
|
||||
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x3C000000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x3C000000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 67108864 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM0 1
|
||||
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
#define XCHAL_HAVE_IDMA_TRANSPOSE 0
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x000637FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00380000
|
||||
#define XCHAL_INTLEVEL3_MASK 0x28C08800
|
||||
#define XCHAL_INTLEVEL4_MASK 0x53000000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x84010000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 1
|
||||
#define XCHAL_INT9_LEVEL 1
|
||||
#define XCHAL_INT10_LEVEL 1
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 1
|
||||
#define XCHAL_INT13_LEVEL 1
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 3
|
||||
#define XCHAL_INT16_LEVEL 5
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 2
|
||||
#define XCHAL_INT20_LEVEL 2
|
||||
#define XCHAL_INT21_LEVEL 2
|
||||
#define XCHAL_INT22_LEVEL 3
|
||||
#define XCHAL_INT23_LEVEL 3
|
||||
#define XCHAL_INT24_LEVEL 4
|
||||
#define XCHAL_INT25_LEVEL 4
|
||||
#define XCHAL_INT26_LEVEL 5
|
||||
#define XCHAL_INT27_LEVEL 3
|
||||
#define XCHAL_INT28_LEVEL 4
|
||||
#define XCHAL_INT29_LEVEL 3
|
||||
#define XCHAL_INT30_LEVEL 4
|
||||
#define XCHAL_INT31_LEVEL 5
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 11
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
|
||||
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
|
||||
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
|
||||
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
|
||||
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
|
||||
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
|
||||
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
|
||||
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
|
||||
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
|
||||
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
|
||||
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
|
||||
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
|
||||
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
|
||||
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x40000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x40000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
|
||||
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
@@ -0,0 +1,493 @@
|
||||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2021 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
// #define XTENSA_CONFIG_VERSION 0x60
|
||||
|
||||
// #include "xtensa-config.h"
|
||||
// #include "xtensa-tdep.h"
|
||||
|
||||
|
||||
|
||||
// /* Masked registers. */
|
||||
// xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
|
||||
// xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
|
||||
// xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
|
||||
// xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
|
||||
// xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
|
||||
// xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
|
||||
// xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
|
||||
// xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
|
||||
// xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
|
||||
// xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
|
||||
// xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
|
||||
// xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
|
||||
// xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
|
||||
// xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
|
||||
// xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
|
||||
// xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
|
||||
// xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };
|
||||
// const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
|
||||
// xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
|
||||
// xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
|
||||
// xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
|
||||
// xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };
|
||||
// const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
|
||||
// xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };
|
||||
// const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
|
||||
// xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78, 0, 8 } };
|
||||
// const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
|
||||
// xtensa_reg_mask_t xtensa_submask23[] = { { 167, 8, 4 } };
|
||||
// const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
|
||||
// xtensa_reg_mask_t xtensa_submask24[] = { { 100, 0, 2 } };
|
||||
// const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
|
||||
// xtensa_reg_mask_t xtensa_submask25[] = { { 100, 6, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
|
||||
// xtensa_reg_mask_t xtensa_submask26[] = { { 100, 5, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
|
||||
// xtensa_reg_mask_t xtensa_submask27[] = { { 100, 4, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
|
||||
// xtensa_reg_mask_t xtensa_submask28[] = { { 100, 3, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
|
||||
// xtensa_reg_mask_t xtensa_submask29[] = { { 100, 2, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
|
||||
// xtensa_reg_mask_t xtensa_submask30[] = { { 101, 11, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
|
||||
// xtensa_reg_mask_t xtensa_submask31[] = { { 101, 10, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
|
||||
// xtensa_reg_mask_t xtensa_submask32[] = { { 101, 9, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
|
||||
// xtensa_reg_mask_t xtensa_submask33[] = { { 101, 8, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
|
||||
// xtensa_reg_mask_t xtensa_submask34[] = { { 101, 7, 1 } };
|
||||
// const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
|
||||
// xtensa_reg_mask_t xtensa_submask35[] = { { 100, 12, 20 } };
|
||||
// const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
|
||||
// xtensa_reg_mask_t xtensa_submask36[] = { { 101, 12, 20 } };
|
||||
// const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
|
||||
// xtensa_reg_mask_t xtensa_submask37[] = { { 100, 7, 5 } };
|
||||
// const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
|
||||
// xtensa_reg_mask_t xtensa_submask38[] = { { 101, 0, 7 } };
|
||||
// const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
|
||||
// xtensa_reg_mask_t xtensa_submask39[] = { { 102, 0, 32 }, { 103, 0, 8 } };
|
||||
// const xtensa_mask_t xtensa_mask39 = { 2, xtensa_submask39 };
|
||||
// xtensa_reg_mask_t xtensa_submask40[] = { { 104, 0, 32 }, { 105, 0, 32 }, { 106, 0, 32 }, { 107, 0, 32 }, { 108, 0, 32 } };
|
||||
// const xtensa_mask_t xtensa_mask40 = { 5, xtensa_submask40 };
|
||||
// xtensa_reg_mask_t xtensa_submask41[] = { { 109, 0, 32 }, { 110, 0, 32 }, { 111, 0, 32 }, { 112, 0, 32 }, { 113, 0, 32 } };
|
||||
// const xtensa_mask_t xtensa_mask41 = { 5, xtensa_submask41 };
|
||||
// xtensa_reg_mask_t xtensa_submask42[] = { { 116, 0, 32 }, { 117, 0, 32 }, { 118, 0, 32 }, { 119, 0, 32 } };
|
||||
// const xtensa_mask_t xtensa_mask42 = { 4, xtensa_submask42 };
|
||||
|
||||
|
||||
// /* Register map. */
|
||||
// xtensa_register_t rmap[] =
|
||||
// {
|
||||
/* idx ofs bi sz al targno flags cp typ group name */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0)
|
||||
XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0)
|
||||
XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0)
|
||||
XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0)
|
||||
XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0)
|
||||
XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0)
|
||||
XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0)
|
||||
XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
|
||||
XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
|
||||
XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
|
||||
XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
|
||||
XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
|
||||
XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
|
||||
XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
|
||||
XTREG( 83,332, 8, 4, 4,0x030c,0x000e,-1, 3,0x0210,gpio_out, 0,0,0,0,0,0)
|
||||
XTREG( 84,336,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
|
||||
"03:03:44:00","03:03:04:00",0,0,0,0)
|
||||
XTREG( 85,340,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
|
||||
"03:13:44:00","03:13:04:00",0,0,0,0)
|
||||
XTREG( 86,344,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
|
||||
"03:23:44:00","03:23:04:00",0,0,0,0)
|
||||
XTREG( 87,348,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
|
||||
"03:33:44:00","03:33:04:00",0,0,0,0)
|
||||
XTREG( 88,352,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
|
||||
"03:43:44:00","03:43:04:00",0,0,0,0)
|
||||
XTREG( 89,356,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
|
||||
"03:53:44:00","03:53:04:00",0,0,0,0)
|
||||
XTREG( 90,360,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
|
||||
"03:63:44:00","03:63:04:00",0,0,0,0)
|
||||
XTREG( 91,364,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
|
||||
"03:73:44:00","03:73:04:00",0,0,0,0)
|
||||
XTREG( 92,368,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
|
||||
"03:83:44:00","03:83:04:00",0,0,0,0)
|
||||
XTREG( 93,372,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
|
||||
"03:93:44:00","03:93:04:00",0,0,0,0)
|
||||
XTREG( 94,376,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
|
||||
"03:a3:44:00","03:a3:04:00",0,0,0,0)
|
||||
XTREG( 95,380,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
|
||||
"03:b3:44:00","03:b3:04:00",0,0,0,0)
|
||||
XTREG( 96,384,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
|
||||
"03:c3:44:00","03:c3:04:00",0,0,0,0)
|
||||
XTREG( 97,388,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
|
||||
"03:d3:44:00","03:d3:04:00",0,0,0,0)
|
||||
XTREG( 98,392,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
|
||||
"03:e3:44:00","03:e3:04:00",0,0,0,0)
|
||||
XTREG( 99,396,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
|
||||
"03:f3:44:00","03:f3:04:00",0,0,0,0)
|
||||
XTREG(100,400,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
|
||||
XTREG(101,404,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
|
||||
XTREG(102,408,32, 4, 4,0x0300,0x0006, 3, 3,0x0200,accx_0, 0,0,0,0,0,0)
|
||||
XTREG(103,412, 8, 4, 4,0x0301,0x0006, 3, 3,0x0200,accx_1, 0,0,0,0,0,0)
|
||||
XTREG(104,416,32, 4, 4,0x0302,0x0006, 3, 3,0x0200,qacc_h_0, 0,0,0,0,0,0)
|
||||
XTREG(105,420,32, 4, 4,0x0303,0x0006, 3, 3,0x0200,qacc_h_1, 0,0,0,0,0,0)
|
||||
XTREG(106,424,32, 4, 4,0x0304,0x0006, 3, 3,0x0200,qacc_h_2, 0,0,0,0,0,0)
|
||||
XTREG(107,428,32, 4, 4,0x0305,0x0006, 3, 3,0x0200,qacc_h_3, 0,0,0,0,0,0)
|
||||
XTREG(108,432,32, 4, 4,0x0306,0x0006, 3, 3,0x0200,qacc_h_4, 0,0,0,0,0,0)
|
||||
XTREG(109,436,32, 4, 4,0x0307,0x0006, 3, 3,0x0200,qacc_l_0, 0,0,0,0,0,0)
|
||||
XTREG(110,440,32, 4, 4,0x0308,0x0006, 3, 3,0x0200,qacc_l_1, 0,0,0,0,0,0)
|
||||
XTREG(111,444,32, 4, 4,0x0309,0x0006, 3, 3,0x0200,qacc_l_2, 0,0,0,0,0,0)
|
||||
XTREG(112,448,32, 4, 4,0x030a,0x0006, 3, 3,0x0200,qacc_l_3, 0,0,0,0,0,0)
|
||||
XTREG(113,452,32, 4, 4,0x030b,0x0006, 3, 3,0x0200,qacc_l_4, 0,0,0,0,0,0)
|
||||
XTREG(114,456, 4, 4, 4,0x030d,0x0006, 3, 3,0x0210,sar_byte, 0,0,0,0,0,0)
|
||||
XTREG(115,460, 4, 4, 4,0x030e,0x0006, 3, 3,0x0210,fft_bit_width,0,0,0,0,0,0)
|
||||
XTREG(116,464,32, 4, 4,0x030f,0x0006, 3, 3,0x0200,ua_state_0, 0,0,0,0,0,0)
|
||||
XTREG(117,468,32, 4, 4,0x0310,0x0006, 3, 3,0x0200,ua_state_1, 0,0,0,0,0,0)
|
||||
XTREG(118,472,32, 4, 4,0x0311,0x0006, 3, 3,0x0200,ua_state_2, 0,0,0,0,0,0)
|
||||
XTREG(119,476,32, 4, 4,0x0312,0x0006, 3, 3,0x0200,ua_state_3, 0,0,0,0,0,0)
|
||||
XTREG(120,480,128,16,16,0x1008,0x0006, 3, 4,0x0201,q0,
|
||||
"03:44:60:cd","03:44:20:cd",0,0,0,0)
|
||||
XTREG(121,496,128,16,16,0x1009,0x0006, 3, 4,0x0201,q1,
|
||||
"03:44:e0:cd","03:44:a0:cd",0,0,0,0)
|
||||
XTREG(122,512,128,16,16,0x100a,0x0006, 3, 4,0x0201,q2,
|
||||
"03:44:60:dd","03:44:20:dd",0,0,0,0)
|
||||
XTREG(123,528,128,16,16,0x100b,0x0006, 3, 4,0x0201,q3,
|
||||
"03:44:e0:dd","03:44:a0:dd",0,0,0,0)
|
||||
XTREG(124,544,128,16,16,0x100c,0x0006, 3, 4,0x0201,q4,
|
||||
"03:44:60:ed","03:44:20:ed",0,0,0,0)
|
||||
XTREG(125,560,128,16,16,0x100d,0x0006, 3, 4,0x0201,q5,
|
||||
"03:44:e0:ed","03:44:a0:ed",0,0,0,0)
|
||||
XTREG(126,576,128,16,16,0x100e,0x0006, 3, 4,0x0201,q6,
|
||||
"03:44:60:fd","03:44:20:fd",0,0,0,0)
|
||||
XTREG(127,592,128,16,16,0x100f,0x0006, 3, 4,0x0201,q7,
|
||||
"03:44:e0:fd","03:44:a0:fd",0,0,0,0)
|
||||
XTREG(128,608,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG(129,612, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG(130,616, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0)
|
||||
XTREG(131,620, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG(132,624,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG(133,628,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG(134,632,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG(135,636,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG(136,640,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG(137,644,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG(138,648,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG(139,652,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG(140,656,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG(141,660,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG(142,664,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG(143,668,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG(144,672,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG(145,676,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG(146,680,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG(147,684,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG(148,688,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG(149,692,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG(150,696,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG(151,700,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG(152,704,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG(153,708,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG(154,712,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG(155,716,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG(156,720,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG(157,724,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG(158,728,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG(159,732,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG(160,736, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG(161,740,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG(162,744,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG(163,748,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG(164,752,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG(165,756,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG(166,760, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG(167,764,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG(168,768,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG(169,772,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG(170,776,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG(171,780, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG(172,784,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(173,788,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(174,792,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(175,796,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG(176,800,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG(177,804,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG(178,808,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, 0,0,0,0,0,0)
|
||||
XTREG(179,812,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, 0,0,0,0,0,0)
|
||||
XTREG(180,816,32, 4, 4,0x2028,0x000f,-2, 4,0x0101,pwrctl,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(181,820,32, 4, 4,0x2029,0x000f,-2, 4,0x0101,pwrstat,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(182,824, 1, 4, 4,0x202a,0x000f,-2, 4,0x0101,eristat,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(183,828,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,cs_itctrl,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(184,832,16, 4, 4,0x202c,0x000f,-2, 4,0x0101,cs_claimset,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(185,836,16, 4, 4,0x202d,0x000f,-2, 4,0x0101,cs_claimclr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(186,840,32, 4, 4,0x202e,0x000d,-2, 4,0x0101,cs_lockaccess,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(187,844,32, 4, 4,0x202f,0x000b,-2, 4,0x0101,cs_lockstatus,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(188,848, 1, 4, 4,0x2030,0x000b,-2, 4,0x0101,cs_authstatus,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(189,852,32, 4, 4,0x203f,0x000f,-2, 4,0x0101,fault_info,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(190,856,32, 4, 4,0x2040,0x0003,-2, 4,0x0101,trax_id,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(191,860,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,trax_control,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(192,864,32, 4, 4,0x2042,0x000b,-2, 4,0x0101,trax_status,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(193,868,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,trax_data,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(194,872,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,trax_address,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(195,876,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,trax_pctrigger,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(196,880,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,trax_pcmatch,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(197,884,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,trax_delay,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(198,888,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,trax_memstart,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(199,892,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,trax_memend,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(200,896,32, 4, 4,0x2057,0x000f,-2, 4,0x0101,pmg,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(201,900,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmpc,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(202,904,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pm0,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(203,908,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pm1,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(204,912,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pmctrl0,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(205,916,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pmctrl1,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(206,920,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,pmstat0,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(207,924,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,pmstat1,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(208,928,32, 4, 4,0x205f,0x0003,-2, 4,0x0101,ocdid,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(209,932,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,ocd_dcrclr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(210,936,32, 4, 4,0x2061,0x000f,-2, 4,0x0101,ocd_dcrset,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(211,940,32, 4, 4,0x2062,0x000f,-2, 4,0x0101,ocd_dsr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(212,944,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0)
|
||||
XTREG(213,948,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0)
|
||||
XTREG(214,952,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0)
|
||||
XTREG(215,956,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0)
|
||||
XTREG(216,960,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0)
|
||||
XTREG(217,964,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0)
|
||||
XTREG(218,968,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0)
|
||||
XTREG(219,972,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0)
|
||||
XTREG(220,976,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0)
|
||||
XTREG(221,980,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0)
|
||||
XTREG(222,984,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0)
|
||||
XTREG(223,988,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0)
|
||||
XTREG(224,992,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0)
|
||||
XTREG(225,996,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0)
|
||||
XTREG(226,1000,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0)
|
||||
XTREG(227,1004,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0)
|
||||
XTREG(228,1008, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(229,1009, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(230,1010, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(231,1011, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(232,1012, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(233,1013, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(234,1014, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(235,1015, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(236,1016, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(237,1017, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(238,1018, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(239,1019, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(240,1020, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(241,1021, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(242,1022, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(243,1023, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG(244,1024, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask16,0,0,0)
|
||||
XTREG(245,1028, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask17,0,0,0)
|
||||
XTREG(246,1032, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask18,0,0,0)
|
||||
XTREG(247,1036, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask19,0,0,0)
|
||||
XTREG(248,1040, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask20,0,0,0)
|
||||
XTREG(249,1044, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask21,0,0,0)
|
||||
XTREG(250,1048,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
|
||||
0,0,&xtensa_mask22,0,0,0)
|
||||
XTREG(251,1056, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask23,0,0,0)
|
||||
XTREG(252,1060, 2, 4, 4,0x2015,0x0006, 0, 5,0x1010,roundmode,
|
||||
0,0,&xtensa_mask24,0,0,0)
|
||||
XTREG(253,1064, 1, 4, 4,0x2016,0x0006, 0, 5,0x1010,invalidenable,
|
||||
0,0,&xtensa_mask25,0,0,0)
|
||||
XTREG(254,1068, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,divzeroenable,
|
||||
0,0,&xtensa_mask26,0,0,0)
|
||||
XTREG(255,1072, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,overflowenable,
|
||||
0,0,&xtensa_mask27,0,0,0)
|
||||
XTREG(256,1076, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,underflowenable,
|
||||
0,0,&xtensa_mask28,0,0,0)
|
||||
XTREG(257,1080, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,inexactenable,
|
||||
0,0,&xtensa_mask29,0,0,0)
|
||||
XTREG(258,1084, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,invalidflag,
|
||||
0,0,&xtensa_mask30,0,0,0)
|
||||
XTREG(259,1088, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,divzeroflag,
|
||||
0,0,&xtensa_mask31,0,0,0)
|
||||
XTREG(260,1092, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,overflowflag,
|
||||
0,0,&xtensa_mask32,0,0,0)
|
||||
XTREG(261,1096, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,underflowflag,
|
||||
0,0,&xtensa_mask33,0,0,0)
|
||||
XTREG(262,1100, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,inexactflag,
|
||||
0,0,&xtensa_mask34,0,0,0)
|
||||
XTREG(263,1104,20, 4, 4,0x2020,0x0006, 0, 5,0x1010,fpreserved20,
|
||||
0,0,&xtensa_mask35,0,0,0)
|
||||
XTREG(264,1108,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20a,
|
||||
0,0,&xtensa_mask36,0,0,0)
|
||||
XTREG(265,1112, 5, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved5,
|
||||
0,0,&xtensa_mask37,0,0,0)
|
||||
XTREG(266,1116, 7, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved7,
|
||||
0,0,&xtensa_mask38,0,0,0)
|
||||
XTREG(267,1120,40, 8, 4,0x2024,0x0006, 3, 5,0x0210,accx,
|
||||
0,0,&xtensa_mask39,0,0,0)
|
||||
XTREG(268,1128,160,20, 4,0x2025,0x0006, 3, 5,0x0210,qacc_h,
|
||||
0,0,&xtensa_mask40,0,0,0)
|
||||
XTREG(269,1148,160,20, 4,0x2026,0x0006, 3, 5,0x0210,qacc_l,
|
||||
0,0,&xtensa_mask41,0,0,0)
|
||||
XTREG_END
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -9,3 +9,4 @@ core-sample_controller.c
|
||||
core-test_kc705_be.c
|
||||
core-test_mmuhifi_c3.c
|
||||
core-esp32.c
|
||||
core-esp32s3.c
|
||||
|
||||
Reference in New Issue
Block a user