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target/i386: Add get/set/migrate support for FRED MSRs

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FRED CPU states are managed in 9 new FRED MSRs, in addtion to a few
existing CPU registers and MSRs, e.g., CR4.FRED and MSR_IA32_PL0_SSP.

Save/restore/migrate FRED MSRs if FRED is exposed to the guest.

Tested-by: Shan Kang <shan.kang@intel.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Message-ID: <20231109072012.8078-7-xin3.li@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Xin Li
2023-11-08 23:20:12 -08:00
committed by Paolo Bonzini
parent ef202d64c3
commit 4ebd98eb3a
3 changed files with 99 additions and 0 deletions
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target/i386/cpu.h
+22
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@@ -538,6 +538,17 @@ typedef enum X86Seg {
#define MSR_IA32_XFD 0x000001c4
#define MSR_IA32_XFD_ERR 0x000001c5
/* FRED MSRs */
#define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */
#define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */
#define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */
#define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 regular stack pointer */
#define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception stack levels */
#define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in ring 0 */
#define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 shadow stack pointer in ring 0 */
#define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in ring 0 */
#define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack level */
#define MSR_IA32_BNDCFGS 0x00000d90
#define MSR_IA32_XSS 0x00000da0
#define MSR_IA32_UMWAIT_CONTROL 0xe1
@@ -1723,6 +1734,17 @@ typedef struct CPUArchState {
target_ulong cstar;
target_ulong fmask;
target_ulong kernelgsbase;
/* FRED MSRs */
uint64_t fred_rsp0;
uint64_t fred_rsp1;
uint64_t fred_rsp2;
uint64_t fred_rsp3;
uint64_t fred_stklvls;
uint64_t fred_ssp1;
uint64_t fred_ssp2;
uint64_t fred_ssp3;
uint64_t fred_config;
#endif
uint64_t tsc_adjust;