From 55d801ca9e60eb754b68975509e001dec76e82a7 Mon Sep 17 00:00:00 2001 From: Evan Reichard Date: Sun, 26 Jul 2026 09:27:15 -0400 Subject: [PATCH] refactor(xteink): drop no-op JTAG interrupt clear handling --- hw/misc/esp32c3_jtag.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/misc/esp32c3_jtag.c b/hw/misc/esp32c3_jtag.c index a6c060ac2c..cea07feac4 100644 --- a/hw/misc/esp32c3_jtag.c +++ b/hw/misc/esp32c3_jtag.c @@ -23,11 +23,11 @@ #define ESP32C3_JTAG_INT_RAW_REG 0x08 #define ESP32C3_JTAG_INT_ST_REG 0x0c #define ESP32C3_JTAG_INT_ENA_REG 0x10 -#define ESP32C3_JTAG_INT_CLR_REG 0x14 #define ESP32C3_JTAG_IN_EP_DATA_FREE (1u << 1) #define ESP32C3_JTAG_SOF_INT (1u << 1) #define ESP32C3_JTAG_SERIAL_IN_EMPTY (1u << 3) +/* ponytail: interrupts are permanently pending - the tap has no real FIFO or USB host, so SOF and SERIAL_IN_EMPTY are always true and INT_CLR is a no-op. Model real raw/clear state if a driver ever needs an edge. */ static uint32_t esp32c3_jtag_raw_interrupts(void) { return ESP32C3_JTAG_SOF_INT | ESP32C3_JTAG_SERIAL_IN_EMPTY; @@ -66,9 +66,6 @@ static void esp32c3_jtag_write(void *opaque, hwaddr addr, uint64_t value, unsign s->int_ena = value; esp32c3_jtag_update_irq(s); break; - case ESP32C3_JTAG_INT_CLR_REG: - esp32c3_jtag_update_irq(s); - break; default: break; }