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target/xtensa: add stubs for DFP Accelerator instructions

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Ivan Grokhotkov
2019-08-08 17:21:51 +02:00
parent fa4675662e
commit 6f40683a92
1 changed files with 24 additions and 0 deletions
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target/xtensa/translate.c
+24
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@@ -2624,6 +2624,12 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
} }
static void translate_xur_f64(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
/* no-op */
}
static void translate_xor(DisasContext *dc, const OpcodeArg arg[], static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]) const uint32_t par[])
{ {
@@ -5395,6 +5401,24 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "wur.expstate", .name = "wur.expstate",
.translate = translate_wur, .translate = translate_wur,
.par = (const uint32_t[]){EXPSTATE}, .par = (const uint32_t[]){EXPSTATE},
}, {
.name = "wur.f64r_lo",
.translate = translate_xur_f64,
}, {
.name = "wur.f64r_hi",
.translate = translate_xur_f64,
}, {
.name = "wur.f64s",
.translate = translate_xur_f64,
}, {
.name = "rur.f64r_lo",
.translate = translate_xur_f64,
}, {
.name = "rur.f64r_hi",
.translate = translate_xur_f64,
}, {
.name = "rur.f64s",
.translate = translate_xur_f64,
}, { }, {
.name = "wur.threadptr", .name = "wur.threadptr",
.translate = translate_wur, .translate = translate_wur,