From 9607e2625492aadbd69958c1a1314d20e97d5675 Mon Sep 17 00:00:00 2001
From: Omar Chebib <omar.chebib@espressif.com>
Date: Tue, 25 Mar 2025 17:42:45 +0800
Subject: [PATCH] esp32: refactor drivers to use three-stage reset instead of
 legacy reset

---
 hw/char/esp32_uart.c       | 7 ++++---
 hw/gpio/esp32_gpio.c       | 5 +++--
 hw/i2c/esp32_i2c.c         | 8 ++++----
 hw/misc/esp32_aes.c        | 9 ++++-----
 hw/misc/esp32_dport.c      | 7 ++++---
 hw/misc/esp32_flash_enc.c  | 9 ++++-----
 hw/misc/esp32_rsa.c        | 9 ++++-----
 hw/misc/esp32_rtc_cntl.c   | 7 ++++---
 hw/nvram/esp32_efuse.c     | 7 ++++---
 hw/ssi/esp32_spi.c         | 7 ++++---
 hw/timer/esp32_frc_timer.c | 8 ++++----
 hw/timer/esp32_timg.c      | 7 ++++---
 hw/xtensa/esp32_intc.c     | 9 +++++----
 13 files changed, 52 insertions(+), 47 deletions(-)

diff --git a/hw/char/esp32_uart.c b/hw/char/esp32_uart.c
index f6be08dd3e..41de9cf80f 100644
--- a/hw/char/esp32_uart.c
+++ b/hw/char/esp32_uart.c
@@ -309,9 +309,9 @@ static void uart_rx_timeout_timer_cb(void* opaque)
     esp32_uart_update_irq(s);
 }
 
-static void esp32_uart_reset(DeviceState *dev)
+static void esp32_uart_reset_hold(Object *obj, ResetType type)
 {
-    ESP32UARTState *s = ESP32_UART(dev);
+    ESP32UARTState *s = ESP32_UART(obj);
 
     memset(s->reg, 0, sizeof(s->reg));
     s->reg[R_UART_RXD_CNT] = 0;
@@ -379,12 +379,13 @@ static void esp32_uart_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     ESP32UARTClass *class = ESP32_UART_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
     /* Populate the virtual attributes and methods here (if any) */
     class->uart_write = uart_write;
     class->uart_read = uart_read;
 
-    dc->legacy_reset = esp32_uart_reset;
+    rc->phases.hold = esp32_uart_reset_hold;
     dc->realize = esp32_uart_realize;
     device_class_set_props(dc, esp32_uart_properties);
 }
diff --git a/hw/gpio/esp32_gpio.c b/hw/gpio/esp32_gpio.c
index 0b3b47623e..4fea1f5cc7 100644
--- a/hw/gpio/esp32_gpio.c
+++ b/hw/gpio/esp32_gpio.c
@@ -47,7 +47,7 @@ static const MemoryRegionOps uart_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_gpio_reset(DeviceState *dev)
+static void esp32_gpio_reset_hold(Object *obj, ResetType type)
 {
 }
 
@@ -79,8 +79,9 @@ static Property esp32_gpio_properties[] = {
 static void esp32_gpio_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_gpio_reset;
+    rc->phases.hold = esp32_gpio_reset_hold;
     dc->realize = esp32_gpio_realize;
     device_class_set_props(dc, esp32_gpio_properties);
 }
diff --git a/hw/i2c/esp32_i2c.c b/hw/i2c/esp32_i2c.c
index ea0131c911..5f4022f0b1 100644
--- a/hw/i2c/esp32_i2c.c
+++ b/hw/i2c/esp32_i2c.c
@@ -8,9 +8,9 @@
 static void esp32_i2c_do_transaction(Esp32I2CState * s);
 static void esp32_i2c_update_irq(Esp32I2CState * s);
 
-static void esp32_i2c_reset(DeviceState * dev)
+static void esp32_i2c_reset_hold(Object *obj, ResetType type)
 {
-    Esp32I2CState * s = Esp32_I2C(dev);
+    Esp32I2CState * s = Esp32_I2C(obj);
 
     fifo8_reset(&s->rx_fifo);
     fifo8_reset(&s->tx_fifo);
@@ -263,8 +263,8 @@ static void esp32_i2c_init(Object * obj)
 
 static void esp32_i2c_class_init(ObjectClass * klass, void * data)
 {
-    DeviceClass * dc = DEVICE_CLASS(klass);
-    dc->legacy_reset = esp32_i2c_reset;
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    rc->phases.hold = esp32_i2c_reset_hold;
 }
 
 static const TypeInfo esp32_i2c_type_info = {
diff --git a/hw/misc/esp32_aes.c b/hw/misc/esp32_aes.c
index 82c3872a30..43d70cf117 100644
--- a/hw/misc/esp32_aes.c
+++ b/hw/misc/esp32_aes.c
@@ -90,9 +90,9 @@ static const MemoryRegionOps esp32_aes_ops = {
         .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_aes_reset(DeviceState *dev)
+static void esp32_aes_reset_hold(Object *obj, ResetType type)
 {
-    Esp32AesState *s = ESP32_AES(dev);
+    Esp32AesState *s = ESP32_AES(obj);
     s->aes_idle_reg = 0;
 }
 
@@ -108,9 +108,8 @@ static void esp32_aes_init(Object *obj)
 
 static void esp32_aes_class_init(ObjectClass *klass, void *data)
 {
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->legacy_reset = esp32_aes_reset;
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    rc->phases.hold = esp32_aes_reset_hold;
 }
 
 static const TypeInfo esp32_aes_info = {
diff --git a/hw/misc/esp32_dport.c b/hw/misc/esp32_dport.c
index ee3e68bb58..1bb2435f48 100644
--- a/hw/misc/esp32_dport.c
+++ b/hw/misc/esp32_dport.c
@@ -364,9 +364,9 @@ static const MemoryRegionOps esp32_cache_ill_trap_ops = {
     .write = esp32_cache_ill_write,
 };
 
-static void esp32_dport_reset(DeviceState *dev)
+static void esp32_dport_reset_hold(Object *obj, ResetType type)
 {
-    Esp32DportState *s = ESP32_DPORT(dev);
+    Esp32DportState *s = ESP32_DPORT(obj);
 
     s->appcpu_boot_addr = 0;
     s->appcpu_clkgate_state = false;
@@ -454,8 +454,9 @@ static Property esp32_dport_properties[] = {
 static void esp32_dport_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_dport_reset;
+    rc->phases.hold = esp32_dport_reset_hold;
     dc->realize = esp32_dport_realize;
     device_class_set_props(dc, esp32_dport_properties);
 }
diff --git a/hw/misc/esp32_flash_enc.c b/hw/misc/esp32_flash_enc.c
index 8430e113be..54dfee1a1b 100644
--- a/hw/misc/esp32_flash_enc.c
+++ b/hw/misc/esp32_flash_enc.c
@@ -242,17 +242,16 @@ static void esp32_flash_encryption_init(Object *obj)
     sysbus_init_mmio(sbd, &s->iomem);
 }
 
-static void esp32_flash_encryption_reset(DeviceState *dev)
+static void esp32_flash_encryption_reset_hold(Object *obj, ResetType type)
 {
-    Esp32FlashEncryptionState *s = ESP32_FLASH_ENCRYPTION(dev);
+    Esp32FlashEncryptionState *s = ESP32_FLASH_ENCRYPTION(obj);
     s->encryption_done = false;
 }
 
 static void esp32_flash_encryption_class_init(ObjectClass *klass, void *data)
 {
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->legacy_reset = esp32_flash_encryption_reset;
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    rc->phases.hold = esp32_flash_encryption_reset_hold;
 }
 
 static const TypeInfo esp32_flash_encryption_info = {
diff --git a/hw/misc/esp32_rsa.c b/hw/misc/esp32_rsa.c
index 1c57785ad1..be168bdc65 100644
--- a/hw/misc/esp32_rsa.c
+++ b/hw/misc/esp32_rsa.c
@@ -319,9 +319,9 @@ static const MemoryRegionOps esp32_rsa_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_rsa_reset(DeviceState *dev)
+static void esp32_rsa_reset_hold(Object *obj, ResetType type)
 {
-    Esp32RsaState *s = ESP32_RSA(dev);
+    Esp32RsaState *s = ESP32_RSA(obj);
 
     esp32_rsa_clean_mem(s);
 
@@ -344,9 +344,8 @@ static void esp32_rsa_init(Object *obj)
 
 static void esp32_rsa_class_init(ObjectClass *klass, void *data)
 {
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->legacy_reset = esp32_rsa_reset;
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    rc->phases.hold = esp32_rsa_reset_hold;
 }
 
 static const TypeInfo esp32_rsa_info = {
diff --git a/hw/misc/esp32_rtc_cntl.c b/hw/misc/esp32_rtc_cntl.c
index d3e8d89f30..5e437320e0 100644
--- a/hw/misc/esp32_rtc_cntl.c
+++ b/hw/misc/esp32_rtc_cntl.c
@@ -177,9 +177,9 @@ static const MemoryRegionOps esp32_rtc_cntl_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_rtc_cntl_reset(DeviceState *dev)
+static void esp32_rtc_cntl_reset_hold(Object *obj, ResetType type)
 {
-    Esp32RtcCntlState *s = ESP32_RTC_CNTL(dev);
+    Esp32RtcCntlState *s = ESP32_RTC_CNTL(obj);
 
     s->time_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 }
@@ -222,8 +222,9 @@ static Property esp32_rtc_cntl_properties[] = {
 static void esp32_rtc_cntl_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_rtc_cntl_reset;
+    rc->phases.hold = esp32_rtc_cntl_reset_hold;
     dc->realize = esp32_rtc_cntl_realize;
     device_class_set_props(dc, esp32_rtc_cntl_properties);
 }
diff --git a/hw/nvram/esp32_efuse.c b/hw/nvram/esp32_efuse.c
index a0acfd54f2..c540cb9601 100644
--- a/hw/nvram/esp32_efuse.c
+++ b/hw/nvram/esp32_efuse.c
@@ -237,9 +237,9 @@ static const MemoryRegionOps esp32_efuse_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_efuse_reset(DeviceState *dev)
+static void esp32_efuse_reset_hold(Object *obj, ResetType type)
 {
-    Esp32EfuseState *s = ESP32_EFUSE(dev);
+    Esp32EfuseState *s = ESP32_EFUSE(obj);
     esp32_efuse_read_op(s);
 }
 
@@ -285,8 +285,9 @@ static Property esp32_efuse_properties[] = {
 static void esp32_efuse_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_efuse_reset;
+    rc->phases.hold = esp32_efuse_reset_hold;
     dc->realize = esp32_efuse_realize;
     device_class_set_props(dc, esp32_efuse_properties);
 }
diff --git a/hw/ssi/esp32_spi.c b/hw/ssi/esp32_spi.c
index e310f83888..f47bfca4a8 100644
--- a/hw/ssi/esp32_spi.c
+++ b/hw/ssi/esp32_spi.c
@@ -307,9 +307,9 @@ static const MemoryRegionOps esp32_spi_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_spi_reset(DeviceState *dev)
+static void esp32_spi_reset_hold(Object *obj, ResetType type)
 {
-    Esp32SpiState *s = ESP32_SPI(dev);
+    Esp32SpiState *s = ESP32_SPI(obj);
     s->pin_reg = 0x6;
     s->user1_reg = FIELD_DP32(0, SPI_USER1, ADDR_BITLEN, 23);
     s->user1_reg = FIELD_DP32(s->user1_reg, SPI_USER1, DUMMY_CYCLELEN, 7);
@@ -343,8 +343,9 @@ static Property esp32_spi_properties[] = {
 static void esp32_spi_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_spi_reset;
+    rc->phases.hold = esp32_spi_reset_hold;
     dc->realize = esp32_spi_realize;
     device_class_set_props(dc, esp32_spi_properties);
 }
diff --git a/hw/timer/esp32_frc_timer.c b/hw/timer/esp32_frc_timer.c
index 5ceef82752..8aa80655b1 100644
--- a/hw/timer/esp32_frc_timer.c
+++ b/hw/timer/esp32_frc_timer.c
@@ -181,10 +181,9 @@ static const MemoryRegionOps esp32_frc_timer_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_frc_timer_reset(DeviceState *dev)
+static void esp32_frc_timer_reset_hold(Object *obj, ResetType type)
 {
-    Esp32FrcTimerState *s = ESP32_FRC_TIMER(dev);
-
+    Esp32FrcTimerState *s = ESP32_FRC_TIMER(obj);
     s->prescaler = 1;
 }
 
@@ -223,8 +222,9 @@ static Property esp32_frc_timer_properties[] = {
 static void esp32_frc_timer_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_frc_timer_reset;
+    rc->phases.hold = esp32_frc_timer_reset_hold;
     dc->realize = esp32_frc_timer_realize;
     device_class_set_props(dc, esp32_frc_timer_properties);
 }
diff --git a/hw/timer/esp32_timg.c b/hw/timer/esp32_timg.c
index cd36d084b7..f0f0d6499b 100644
--- a/hw/timer/esp32_timg.c
+++ b/hw/timer/esp32_timg.c
@@ -301,9 +301,9 @@ static void esp32_timg_wdt_reset(Esp32TimgWdtState* ws)
     }
 }
 
-static void esp32_timg_reset(DeviceState *dev)
+static void esp32_timg_reset_hold(Object *obj, ResetType type)
 {
-    Esp32TimgState *s = ESP32_TIMG(dev);
+    Esp32TimgState *s = ESP32_TIMG(obj);
     s->rtc_cal_max = 1;
     s->rtc_cal_clk_sel = ESP32_TIMG_CAL_8MD256;
     s->rtc_cal_ready = 0;
@@ -642,8 +642,9 @@ static Property esp32_timg_properties[] = {
 static void esp32_timg_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_timg_reset;
+    rc->phases.hold = esp32_timg_reset_hold;
     dc->realize = esp32_timg_realize;
     device_class_set_props(dc, esp32_timg_properties);
 }
diff --git a/hw/xtensa/esp32_intc.c b/hw/xtensa/esp32_intc.c
index 7b84e1d4c5..fed7cf7c5b 100644
--- a/hw/xtensa/esp32_intc.c
+++ b/hw/xtensa/esp32_intc.c
@@ -73,9 +73,9 @@ static const MemoryRegionOps esp_intmatrix_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-static void esp32_intmatrix_reset(DeviceState *dev)
+static void esp32_intmatrix_reset_hold(Object *obj, ResetType type)
 {
-    Esp32IntMatrixState *s = ESP32_INTMATRIX(dev);
+    Esp32IntMatrixState *s = ESP32_INTMATRIX(obj);
     memset(s->irq_map, INTMATRIX_UNINT_VALUE, sizeof(s->irq_map));
     for (int i = 0; i < ESP32_CPU_COUNT; ++i) {
         if (s->outputs[i] == NULL) {
@@ -97,7 +97,7 @@ static void esp32_intmatrix_realize(DeviceState *dev, Error **errp)
             s->outputs[i] = xtensa_get_extints(&s->cpu[i]->env);
         }
     }
-    esp32_intmatrix_reset(dev);
+    esp32_intmatrix_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
 }
 
 static void esp32_intmatrix_init(Object *obj)
@@ -121,8 +121,9 @@ static Property esp32_intmatrix_properties[] = {
 static void esp32_intmatrix_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->legacy_reset = esp32_intmatrix_reset;
+    rc->phases.hold = esp32_intmatrix_reset_hold;
     dc->realize = esp32_intmatrix_realize;
     device_class_set_props(dc, esp32_intmatrix_properties);
 }