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tcg/wasm32: add opt-in ramrace guest-RAM/TLB probe

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?ramrace logs off-vCPU guest DRAM reads/writes/maps and TLB flushes. The
open-window crash shows zero such accesses, ruling out IO-thread guest-RAM
access during inflate as the compiled-store corruption source.
This commit is contained in:
Evan Reichard
2026-07-22 23:11:02 -04:00
parent b6d67a89bb
commit ab9c5823ee
2 changed files with 109 additions and 0 deletions
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accel/tcg/cputlb.c
+29
View File
@@ -73,6 +73,28 @@
} \
} while (0)
#if defined(EMSCRIPTEN) && !defined(CONFIG_TCG_INTERPRETER)
extern int wasm_ramrace_trace;
static uint32_t wasm_ramrace_tlb_logs;
static void wasm_ramrace_log_tlb(const char *kind, CPUState *cpu, vaddr addr)
{
if (!wasm_ramrace_trace || current_cpu) {
return;
}
wasm_ramrace_tlb_logs++;
if (wasm_ramrace_tlb_logs <= 200 || (wasm_ramrace_tlb_logs % 10000) == 0) {
printf("RAMRACE tlb-%s off-vcpu #%u tid=%lu cpu=%p addr=0x%llx\n",
kind, wasm_ramrace_tlb_logs, (unsigned long)pthread_self(),
cpu, (unsigned long long)addr);
fflush(stdout);
}
}
#else
#define wasm_ramrace_log_tlb(kind, cpu, addr) ((void)0)
#endif
#define assert_cpu_is_self(cpu) do { \
if (DEBUG_TLB_GATE) { \
g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \
@@ -417,6 +439,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
{
tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap);
wasm_ramrace_log_tlb("full", cpu, 0);
assert_cpu_is_self(cpu);
@@ -433,6 +456,7 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap)
const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work;
tlb_debug("mmu_idx: 0x%"PRIx16"\n", idxmap);
wasm_ramrace_log_tlb("full-all", src_cpu, 0);
flush_all_helper(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap));
async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap));
@@ -608,6 +632,7 @@ static void tlb_flush_page_by_mmuidx_async_2(CPUState *cpu,
void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap)
{
tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%" PRIx16 "\n", addr, idxmap);
wasm_ramrace_log_tlb("page", cpu, addr);
assert_cpu_is_self(cpu);
@@ -627,6 +652,7 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
uint16_t idxmap)
{
tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap);
wasm_ramrace_log_tlb("page-all", src_cpu, addr);
/* This should already be page aligned */
addr &= TARGET_PAGE_MASK;
@@ -777,6 +803,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
{
TLBFlushRangeData d;
wasm_ramrace_log_tlb("range", cpu, addr);
assert_cpu_is_self(cpu);
/*
@@ -817,6 +844,8 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
TLBFlushRangeData d, *p;
CPUState *dst_cpu;
wasm_ramrace_log_tlb("range-all", src_cpu, addr);
/*
* If all bits are significant, and len is small,
* this devolves to tlb_flush_page.