tcg/wasm32: add normal-speed store-TCI bypass and windowed diff2 arming support

Add an opt-in wasm_disable_store_tci() probe so browser tests can run compiled
stores at normal speed without the differential harness. Also let E11 request
no-chain only for TBs inside its PC window, avoiding the global no-chain
watchdog artifact while preserving valid per-window comparisons.

This keeps production store-TCI unchanged unless explicitly disabled.

accel/tcg/cpu-exec.c

@@ -177,8 +177,9 @@ uint32_t curr_cflags(CPUState *cpu)
     }
 
 #if defined(EMSCRIPTEN) && !defined(CONFIG_TCG_INTERPRETER)
-    /* Differential mode runs one TB per dispatch so wasm_cur_tb_pc stays exact. */
-    if (wasm_diff_on()) {
+    /* E10 needs one TB per dispatch so wasm_cur_tb_pc stays exact; E11 keeps
+     * chaining live to avoid watchdog-only slowdowns before the armed window. */
+    if (wasm_diff_needs_nochain()) {
         cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR;
     }
 #endif
@@ -427,6 +428,11 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 
     cflags = curr_cflags(cpu);
+#if defined(EMSCRIPTEN) && !defined(CONFIG_TCG_INTERPRETER)
+    if (wasm_diff_needs_nochain_at(pc)) {
+        cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR;
+    }
+#endif
     if (check_for_breakpoints(cpu, pc, &cflags)) {
         cpu_loop_exit(cpu);
     }
@@ -989,6 +995,11 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
             cflags = cpu->cflags_next_tb;
             if (cflags == -1) {
                 cflags = curr_cflags(cpu);
+#if defined(EMSCRIPTEN) && !defined(CONFIG_TCG_INTERPRETER)
+                if (wasm_diff_needs_nochain_at(pc)) {
+                    cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR;
+                }
+#endif
             } else {
                 cpu->cflags_next_tb = -1;
             }