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Guard esp32c3 cache XTS-AES use when gcrypt absent

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This commit is contained in:
Evan Reichard
2026-07-20 07:25:59 -04:00
parent 1ff6c3a51e
commit cddd964c57
1 changed files with 6 additions and 9 deletions
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hw/misc/esp32c3_cache.c
+6 -9
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@@ -58,7 +58,6 @@ static inline uint32_t esp32c3_read_mmu_value(ESP32C3CacheState *s, hwaddr reg_a
static inline void esp32c3_write_mmu_value(ESP32C3CacheState *s, hwaddr reg_addr, uint32_t value)
{
ESP32C3XtsAesClass *xts_aes_class = ESP32C3_XTS_AES_GET_CLASS(s->xts_aes);
/* Make the assumption that the address is aligned on sizeof(uint32_t) */
const uint32_t index = reg_addr / sizeof(uint32_t);
/* Reserved bits shall always be 0 */
@@ -82,8 +81,12 @@ static inline void esp32c3_write_mmu_value(ESP32C3CacheState *s, hwaddr reg_addr
if (s->flash_blk != NULL) {
blk_pread(s->flash_blk, physical_address, ESP32C3_PAGE_SIZE, cache_data, 0);
}
if (xts_aes_class->is_flash_enc_enabled(s->xts_aes)) {
xts_aes_class->decrypt(s->xts_aes, physical_address, cache_data, ESP32C3_PAGE_SIZE);
// XTS-AES Flash Decryption - Only wired when built with CONFIG_GCRYPT; absent here means flash is treated as unencrypted, matching hardware with flash encryption disabled. Encrypted-flash firmware needs the gcrypt build.
if (s->xts_aes != NULL) {
ESP32C3XtsAesClass *xts_aes_class = ESP32C3_XTS_AES_GET_CLASS(s->xts_aes);
if (xts_aes_class->is_flash_enc_enabled(s->xts_aes)) {
xts_aes_class->decrypt(s->xts_aes, physical_address, cache_data, ESP32C3_PAGE_SIZE);
}
}
}
s->mmu[index].val = e.val;
@@ -225,12 +228,6 @@ static void esp32c3_cache_realize(DeviceState *dev, Error **errp)
/* Initialize the registers */
esp32c3_cache_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
ESP32C3CacheState *s = ESP32C3_CACHE(dev);
/* Make sure XTS_AES was set or issue an error */
if (s->xts_aes == NULL) {
error_report("[CACHE] XTS_AES controller must be set!");
}
}
static void esp32c3_cache_init(Object *obj)