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esp32s3: refactor drivers to use three-stage reset instead of legacy reset

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This commit is contained in:
Omar Chebib
2025-03-25 17:24:12 +08:00
parent 95c74f43e2
commit e0bfd3961f
6 changed files with 28 additions and 22 deletions
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hw/misc/esp32s3_cache.c
+5 -4
View File
@@ -269,9 +269,9 @@ static const MemoryRegionOps esp32s3_cache_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void esp32s3_cache_reset(DeviceState *dev)
static void esp32s3_cache_reset_hold(Object *obj, ResetType type)
{
ESP32S3CacheState *s = ESP32S3_CACHE(dev);
ESP32S3CacheState *s = ESP32S3_CACHE(obj);
memset(s->regs, 0, ESP32S3_CACHE_REG_COUNT * sizeof(*s->regs));
/* Initialize the MMU with invalid entries */
@@ -293,7 +293,7 @@ static void esp32s3_cache_reset(DeviceState *dev)
static void esp32s3_cache_realize(DeviceState *dev, Error **errp)
{
/* Initialize the registers */
esp32s3_cache_reset(dev);
esp32s3_cache_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
ESP32S3CacheState *s = ESP32S3_CACHE(dev);
/* Make sure XTS_AES was set or issue an error */
@@ -352,8 +352,9 @@ static Property esp32s3_cache_properties[] = {
static void esp32s3_cache_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->legacy_reset = esp32s3_cache_reset;
rc->phases.hold = esp32s3_cache_reset_hold;
dc->realize = esp32s3_cache_realize;
device_class_set_props(dc, esp32s3_cache_properties);
}
hw/misc/esp32s3_rtc_cntl.c
+4 -3
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@@ -177,9 +177,9 @@ static const MemoryRegionOps esp32s3_rtc_cntl_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void esp32s3_rtc_cntl_reset(DeviceState *dev)
static void esp32s3_rtc_cntl_reset_hold(Object *obj, ResetType type)
{
Esp32s3RtcCntlState *s = ESP32S3_RTC_CNTL(dev);
Esp32s3RtcCntlState *s = ESP32S3_RTC_CNTL(obj);
s->time_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
@@ -222,8 +222,9 @@ static Property esp32s3_rtc_cntl_properties[] = {
static void esp32s3_rtc_cntl_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->legacy_reset = esp32s3_rtc_cntl_reset;
rc->phases.hold = esp32s3_rtc_cntl_reset_hold;
dc->realize = esp32s3_rtc_cntl_realize;
device_class_set_props(dc, esp32s3_rtc_cntl_properties);
}
hw/misc/esp32s3_xts_aes.c
+4 -3
View File
@@ -365,9 +365,9 @@ static const MemoryRegionOps esp32s3_xts_aes_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void esp32s3_xts_aes_reset(DeviceState *dev)
static void esp32s3_xts_aes_reset_hold(Object *obj, ResetType type)
{
ESP32S3XtsAesState *s = ESP32S3_XTS_AES(dev);
ESP32S3XtsAesState *s = ESP32S3_XTS_AES(obj);
memset(s->plaintext, 0, ESP32S3_XTS_AES_PLAIN_REG_CNT * sizeof(uint32_t));
memset(s->ciphertext, 0, ESP32S3_XTS_AES_PLAIN_REG_CNT * sizeof(uint32_t));
s->state = XTS_AES_IDLE;
@@ -405,9 +405,10 @@ static void esp32s3_xts_aes_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ESP32S3XtsAesClass* esp32s3_xts_aes = ESP32S3_XTS_AES_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = esp32s3_xts_aes_realize;
dc->legacy_reset = esp32s3_xts_aes_reset;
rc->phases.hold = esp32s3_xts_aes_reset_hold;
esp32s3_xts_aes->is_ciphertext_spi_visible = esp32s3_xts_aes_is_ciphertext_spi_visible;
esp32s3_xts_aes->is_flash_enc_enabled = esp32s3_xts_aes_is_flash_enc_enabled;
hw/ssi/esp32s3_spi.c
+5 -4
View File
@@ -453,9 +453,9 @@ static const MemoryRegionOps esp32s3_spi_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void esp32s3_spi_reset(DeviceState *dev)
static void esp32s3_spi_reset_hold(Object *obj, ResetType type)
{
ESP32S3SpiState *s = ESP32S3_SPI(dev);
ESP32S3SpiState *s = ESP32S3_SPI(obj);
memset(s->data_reg, 0, ESP32S3_SPI_BUF_WORDS * sizeof(uint32_t));
s->mem_ctrl1 = FIELD_DP32(s->mem_ctrl1, SPI_MEM_CTRL1, CS_HOLD_DLY_RES, 0x3ff);
s->mem_clock = FIELD_DP32(s->mem_clock, SPI_MEM_CLOCK, CLKCNT_N, 3);
@@ -494,7 +494,7 @@ static void esp32s3_spi_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem);
// sysbus_init_irq(sbd, &s->irq);
esp32s3_spi_reset(DEVICE(s));
esp32s3_spi_reset_hold(obj, RESET_TYPE_COLD);
s->spi = ssi_create_bus(DEVICE(s), "spi");
qdev_init_gpio_out_named(DEVICE(s), &s->cs_gpio[0], SSI_GPIO_CS, ESP32S3_SPI_CS_COUNT);
@@ -507,8 +507,9 @@ static Property esp32s3_spi_properties[] = {
static void esp32s3_spi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->legacy_reset = esp32s3_spi_reset;
rc->phases.hold = esp32s3_spi_reset_hold;
dc->realize = esp32s3_spi_realize;
device_class_set_props(dc, esp32s3_spi_properties);
}
hw/xtensa/esp32s3_clk.c
+5 -4
View File
@@ -111,9 +111,9 @@ static const MemoryRegionOps esp32s3_clock_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void esp32s3_clock_reset(DeviceState *dev)
static void esp32s3_clock_reset_hold(Object *obj, ResetType type)
{
ESP32S3ClockState *s = ESP32S3_CLOCK(dev);
ESP32S3ClockState *s = ESP32S3_CLOCK(obj);
/* On board reset, set the proper clocks and dividers */
s->sysclk = ( 1 << R_SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_SHIFT) |
(ESP32S3_CLK_SEL_PLL << R_SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_SHIFT) |
@@ -134,7 +134,7 @@ static void esp32s3_clock_reset(DeviceState *dev)
static void esp32s3_clock_realize(DeviceState *dev, Error **errp)
{
/* Initialize the registers */
esp32s3_clock_reset(dev);
esp32s3_clock_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
}
static void esp32s3_clock_init(Object *obj)
@@ -156,8 +156,9 @@ static void esp32s3_clock_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ESP32S3ClockClass* esp32s3_clock = ESP32S3_CLOCK_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->legacy_reset = esp32s3_clock_reset;
rc->phases.hold = esp32s3_clock_reset_hold;
dc->realize = esp32s3_clock_realize;
esp32s3_clock->get_ext_dev_enc_dec_ctrl = esp32s3_clock_get_ext_dev_enc_dec_ctrl;
hw/xtensa/esp32s3_intc.c
+5 -4
View File
@@ -82,9 +82,9 @@ static const MemoryRegionOps esp_intmatrix_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void esp32s3_intmatrix_reset(DeviceState *dev)
static void esp32s3_intmatrix_reset_hold(Object *obj, ResetType type)
{
Esp32s3IntMatrixState *s = ESP32S3_INTMATRIX(dev);
Esp32s3IntMatrixState *s = ESP32S3_INTMATRIX(obj);
memset(s->irq_map, INTMATRIX_UNINT_VALUE, sizeof(s->irq_map));
for (int i = 0; i < ESP32S3_CPU_COUNT; ++i) {
if (s->outputs[i] == NULL) {
@@ -105,7 +105,7 @@ static void esp32s3_intmatrix_realize(DeviceState *dev, Error **errp)
s->outputs[i] = xtensa_get_extints(&s->cpu[i]->env);
}
}
esp32s3_intmatrix_reset(dev);
esp32s3_intmatrix_reset_hold(OBJECT(dev), RESET_TYPE_COLD);
}
static void esp32s3_intmatrix_init(Object *obj)
@@ -129,8 +129,9 @@ static Property esp32s3_intmatrix_properties[] = {
static void esp32s3_intmatrix_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->legacy_reset = esp32s3_intmatrix_reset;
rc->phases.hold = esp32s3_intmatrix_reset_hold;
dc->realize = esp32s3_intmatrix_realize;
device_class_set_props(dc, esp32s3_intmatrix_properties);
}