Omar Chebib
319 lines
11 KiB
C
319 lines
11 KiB
C
/*
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* ESP32-C3 GDMA emulation
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*
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* Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "hw/dma/esp32c3_gdma.h"
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#define DIM(arr) (sizeof(arr)/sizeof(*arr))
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#define ESP32C3_GDMA_WARNING 0
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#define ESP32C3_GDMA_DEBUG 0
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typedef struct {
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uint32_t specific;
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uint32_t generic;
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} ESP32C3IntMapping;
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/**
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* @brief Constant mapping used to easily convert an C3 specific interrupt bitmap into a generic
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* interrupt register bitmap.
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*/
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const ESP32C3IntMapping int_mapping[] = {
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{ .specific = R_DMA_INT_RAW_IN_DSCR_EMPTY_MASK, .generic = R_GDMA_INTERRUPT_IN_DSCR_EMPTY_MASK },
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{ .specific = R_DMA_INT_RAW_IN_DSCR_ERR_MASK, .generic = R_GDMA_INTERRUPT_IN_DSCR_ERR_MASK },
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{ .specific = R_DMA_INT_RAW_IN_ERR_EOF_MASK, .generic = R_GDMA_INTERRUPT_IN_ERR_EOF_MASK },
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{ .specific = R_DMA_INT_RAW_IN_SUC_EOF_MASK, .generic = R_GDMA_INTERRUPT_IN_SUC_EOF_MASK },
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{ .specific = R_DMA_INT_RAW_IN_DONE_MASK, .generic = R_GDMA_INTERRUPT_IN_DONE_MASK },
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{ .specific = R_DMA_INT_RAW_OUT_TOTAL_EOF_MASK, .generic = R_GDMA_INTERRUPT_OUT_TOTAL_EOF_MASK },
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{ .specific = R_DMA_INT_RAW_OUT_DSCR_ERR_MASK, .generic = R_GDMA_INTERRUPT_OUT_DSCR_ERR_MASK },
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{ .specific = R_DMA_INT_RAW_OUT_EOF_MASK, .generic = R_GDMA_INTERRUPT_OUT_EOF_MASK },
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{ .specific = R_DMA_INT_RAW_OUT_DONE_MASK, .generic = R_GDMA_INTERRUPT_OUT_DONE_MASK },
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};
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/**
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* @brief Extract and generate a generic interrupt bitmap for IN and OUT channels out of an ESP32-C3 interrupt bitmap.
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* This is necessary since the ESP32-C3 interrupt registers gather both the IN and OUT interrupt status
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* bits in the same register while the generic implementation seperate them into two different registers.
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*/
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static void esp32c3_to_int_bitmask(uint32_t value, uint32_t *in_value, uint32_t *out_value)
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{
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assert(in_value != NULL && out_value != NULL);
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int i = 0;
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/* IN bitmasks are first in the mapping */
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for (i = 0; i < DIM(int_mapping) / 2; i++) {
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if (value & int_mapping[i].specific) {
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*in_value |= int_mapping[i].generic;
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}
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}
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/* OUT bitmasks are following */
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for (; i < DIM(int_mapping); i++) {
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if (value & int_mapping[i].specific) {
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*out_value |= int_mapping[i].generic;
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}
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}
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}
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/**
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* @brief Extract and generate a generic interrupt bitmap for IN and OUT channels out of an ESP32-C3 interrupt bitmap.
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* This is necessary since the ESP32-C3 interrupt registers gather both the IN and OUT interrupt status
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* bits in the same register while the generic implementation seperate them into two different registers.
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*/
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static uint32_t esp32c3_from_int_bitmask(uint32_t in_value, uint32_t out_value)
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{
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int i = 0;
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uint32_t r = 0;
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for (i = 0; i < DIM(int_mapping) / 2; i++) {
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if (in_value & int_mapping[i].generic) {
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r |= int_mapping[i].specific;
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}
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}
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for (; i < DIM(int_mapping); i++) {
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if (out_value & int_mapping[i].generic) {
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r |= int_mapping[i].specific;
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}
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}
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return r;
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}
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/**
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* @brief Get the virtual/generic GDMA register out of an ESP32-C3 GDMA specific interrupt register.
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*/
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static DmaRegister esp32c3_generic_int_reg(uint32_t reg)
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{
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const DmaRegister assoc[] = {
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[R_DMA_INT_RAW] = GDMA_INT_RAW_REG,
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[R_DMA_INT_ST] = GDMA_INT_ST_REG,
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[R_DMA_INT_ENA] = GDMA_INT_ENA_REG,
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[R_DMA_INT_CLR] = GDMA_INT_CLR_REG,
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};
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/* The `reg` is expressed in bytes while in the array, the entries are expressed in words */
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const uint32_t word = reg / sizeof(uint32_t);
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assert(word < DIM(assoc));
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return assoc[word];
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}
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/**
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* @brief Get the virtual/generic GDMA register out of an ESP32-C3 GDMA channel configuration register.
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*/
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static DmaRegister esp32c3_generic_reg(uint32_t reg)
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{
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/* The interrupt registers are not part of this table, they must be treated separately */
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const DmaRegister assoc[] = {
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[R_DMA_CONF0] = GDMA_CONF0_REG,
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[R_DMA_CONF1] = GDMA_CONF1_REG,
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[R_DMA_FIFO_ST] = GDMA_FIFO_ST_REG,
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[R_DMA_POP] = GDMA_POP_REG,
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[R_DMA_LINK] = GDMA_LINK_REG,
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[R_DMA_STATE] = GDMA_STATE_REG,
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[R_DMA_SUC_EOF_DESC] = GDMA_SUC_EOF_DESC_REG,
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[R_DMA_ERR_EOF_DESC] = GDMA_ERR_EOF_DESC_REG,
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[R_DMA_DESC_ADDR] = GDMA_DESC_ADDR_REG,
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[R_DMA_BF0_DESC_ADDR] = GDMA_BF0_DESC_ADDR_REG,
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[R_DMA_BF1_DESC_ADDR] = GDMA_BF1_DESC_ADDR_REG,
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[R_DMA_PRIORITY] = GDMA_PRIORITY_REG,
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[R_DMA_PERI_SEL] = GDMA_PERI_SEL_REG,
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};
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/* The `reg` is expressed in bytes while in the array, the entries are expressed in words */
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const uint32_t word = reg / sizeof(uint32_t);
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if (word >= DIM(assoc)) {
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return GDMA_UNKNOWN;
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}
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return assoc[word];
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}
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static uint32_t esp32c3_read_int_register(ESP32C3GdmaState *s, hwaddr addr)
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{
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/* Check which channel and which direction is being written to */
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const uint32_t chan = addr / DMA_DIR_REGS_SIZE;
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const uint32_t reg = addr % DMA_DIR_REGS_SIZE;
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const uint32_t generic_reg = esp32c3_generic_int_reg(reg);
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uint32_t in_value = esp_gdma_read_chan_register(&s->parent, ESP_GDMA_IN_IDX, chan, generic_reg);
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uint32_t out_value = esp_gdma_read_chan_register(&s->parent, ESP_GDMA_OUT_IDX, chan, generic_reg);
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return esp32c3_from_int_bitmask(in_value, out_value);
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}
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static uint32_t esp32c3_read_chan_register(ESP32C3GdmaState *s, hwaddr addr)
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{
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/* Check which channel and which direction is being written to */
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const uint32_t chan_with_dir = addr / DMA_DIR_REGS_SIZE;
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const uint32_t chan = chan_with_dir >> 1;
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const uint32_t dir = (chan_with_dir & 1) ? ESP_GDMA_OUT_IDX : ESP_GDMA_IN_IDX;
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const uint32_t reg = addr % DMA_DIR_REGS_SIZE;
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return esp_gdma_read_chan_register(&s->parent, dir, chan, esp32c3_generic_reg(reg));
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}
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static uint64_t esp32c3_gdma_read(void *opaque, hwaddr addr, unsigned int size)
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{
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ESP32C3GdmaState *s = ESP32C3_GDMA(opaque);
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ESPGdmaState *parent = &s->parent;
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uint64_t r = 0;
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/* The registers on the ESP32-C3 start with the interrupt registers, then come the misc registers, and
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* finally the channels configurtaion registers */
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switch (addr) {
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case DMA_INT_CHAN_REGS_START ... DMA_INT_CHAN_REGS_END:
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return esp32c3_read_int_register(s, addr - DMA_INT_CHAN_REGS_START);
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case A_DMA_MISC_CONF:
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return esp_gdma_read_register(parent, GDMA_MISC_REG);
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case DMA_CHAN_REGS_START ... DMA_CHAN_REGS_END:
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return esp32c3_read_chan_register(s, addr - DMA_CHAN_REGS_START);
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default:
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/* Unknown or dummy register */
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#if ESP32C3_GDMA_WARNING
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warn_report("[C3][GDMA] Unsupported read to %08lx", addr);
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#endif
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break;
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}
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#if ESP32C3_GDMA_DEBUG
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info_report("[C3][GDMA] Reading from %08lx (%08lx)", addr, r);
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#endif
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return r;
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}
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static void esp32c3_write_int_register(ESP32C3GdmaState *s, hwaddr addr, uint32_t value)
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{
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/* Check which channel and which direction is being written to */
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const uint32_t chan = addr / DMA_DIR_REGS_SIZE;
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const uint32_t reg = addr % DMA_DIR_REGS_SIZE;
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uint32_t in_value = 0;
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uint32_t out_value = 0;
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/* For each direction, convert the C3 interrupt bitmask into a generic bitmask */
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esp32c3_to_int_bitmask(value, &in_value, &out_value);
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esp_gdma_write_chan_register(&s->parent, ESP_GDMA_IN_IDX, chan, esp32c3_generic_int_reg(reg), in_value);
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esp_gdma_write_chan_register(&s->parent, ESP_GDMA_OUT_IDX, chan, esp32c3_generic_int_reg(reg), out_value);
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}
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static void esp32c3_write_chan_register(ESP32C3GdmaState *s, hwaddr addr, uint32_t value)
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{
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/* Check which channel and which direction is being written to */
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const uint32_t chan_with_dir = addr / DMA_DIR_REGS_SIZE;
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const uint32_t chan = chan_with_dir >> 1;
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const uint32_t dir = (chan_with_dir & 1) ? ESP_GDMA_OUT_IDX : ESP_GDMA_IN_IDX;
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const uint32_t reg = addr % DMA_DIR_REGS_SIZE;
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esp_gdma_write_chan_register(&s->parent, dir, chan, esp32c3_generic_reg(reg), value);
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}
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static void esp32c3_gdma_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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ESP32C3GdmaState *s = ESP32C3_GDMA(opaque);
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ESPGdmaState *parent = &s->parent;
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#if ESP32C3_GDMA_DEBUG
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info_report("[C3][GDMA] Writing to %08lx (%08lx)", addr, value);
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#endif
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/* The registers on the ESP32-C3 start with the interrupt registers, then come the misc registers, and
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* finally the channels configurtaion registers */
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switch (addr) {
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case DMA_INT_CHAN_REGS_START ... DMA_INT_CHAN_REGS_END:
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esp32c3_write_int_register(s, addr - DMA_INT_CHAN_REGS_START, (uint32_t) value);
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break;
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case A_DMA_MISC_CONF:
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esp_gdma_write_register(parent, GDMA_MISC_REG, value);
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break;
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case DMA_CHAN_REGS_START ... DMA_CHAN_REGS_END:
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esp32c3_write_chan_register(s, addr - DMA_CHAN_REGS_START, (uint32_t) value);
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break;
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default:
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/* Unknown or dummy register */
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#if ESP32C3_GDMA_WARNING
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warn_report("[C3][GDMA] Unsupported write to %08lx (%08lx)", addr, value);
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#endif
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break;
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}
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}
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static const MemoryRegionOps esp_gdma_ops = {
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.read = esp32c3_gdma_read,
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.write = esp32c3_gdma_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void esp32c3_gdma_init(Object *obj)
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{
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ESP32C3GdmaState *s = ESP32C3_GDMA(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &esp_gdma_ops, s,
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TYPE_ESP32C3_GDMA, ESP32C3_GDMA_REGS_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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/**
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* @brief Check if the given GDMA peripheral is reserved on the ESP32-C3
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*/
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static bool esp32c3_is_periph_invalid(ESPGdmaState *s, GdmaPeripheral per)
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{
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(void) s;
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/* On the ESP32-C3, some peripherals don't exist, mark them as reserved */
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return per == GDMA_SPI3 || per == GDMA_I2S1 || per == GDMA_LCDCAM;
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}
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static void esp32c3_gdma_class_init(ObjectClass *klass, void *data)
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{
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ESPGdmaClass* class = ESP_GDMA_CLASS(klass);
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class->is_periph_invalid = esp32c3_is_periph_invalid;
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class->m_channel_count = ESP32C3_GDMA_CHANNEL_COUNT;
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}
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static const TypeInfo esp32c3_gdma_info = {
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.name = TYPE_ESP32C3_GDMA,
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.parent = TYPE_ESP_GDMA,
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.instance_size = sizeof(ESP32C3GdmaState),
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.instance_init = esp32c3_gdma_init,
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.class_init = esp32c3_gdma_class_init,
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.class_size = sizeof(ESP32C3GdmaClass)
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};
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static void esp32c3_gdma_register_types(void)
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{
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type_register_static(&esp32c3_gdma_info);
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}
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type_init(esp32c3_gdma_register_types)
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