Omar Chebib
522 lines
15 KiB
C
522 lines
15 KiB
C
/*
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* ESP-PSRAM basic emulation
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*
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* Copyright (c) 2021-2024 Espressif Systems (Shanghai) Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/ssi_psram.h"
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#define PSRAM_WARNING 0
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typedef enum PsramCMD {
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NOP = 0x00,
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READ = 0x03,
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FAST_READ = 0x0B,
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FAST_READ_QUAD = 0xEB,
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WRITE = 0x02,
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QUAD_WRITE = 0x38,
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ENTER_QUAD_MODE = 0x35,
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EXIT_QUAD_MODE = 0xF5,
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RESET_ENABLE = 0x66,
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RESET = 0x99,
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SET_BURST_LENGTH = 0xC0,
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READ_ID = 0x9F,
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/* Octal PSRAM commands */
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OCT_READ_REG = 0x4040,
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OCT_WRITE_REG = 0xc0c0,
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OCT_READ_SYNC = 0x0000,
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OCT_WRITE_SYNC = 0x8080,
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OCT_READ_LINEAR = 0x2020,
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OCT_WRITE_LINEAR = 0xA0A0,
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} PsramCMD;
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/* If the manufacturer ID is 0xd, all the 8MB PSRAMs are in fact 4MB underneath
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* So use another manufacturer ID. */
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#define PSRAM_ID_MFG 0xff
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#define PSRAM_ID_KGD 0x5d
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#define MR0_GET_RD_LATENCY(v) (((v) >> 2) & 0x7)
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#define MR0_DRIVE_STRENGHT_HALF ((uint8_t)0b01 << 0)
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#define MR0_RD_LATENCY_CODE ((uint8_t)0b010 << 2)
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#define MR0_RD_LT_VARIABLE ((uint8_t)0b0 << 5)
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#define MR1_VENDOR_ID ((uint8_t)0b01101 << 0)
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#define MR1_NO_ULP ((uint8_t)0b0 << 5)
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#define MR2_DENSITY_MASK ((uint8_t)0b111 << 0)
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#define MR2_DEVICE_ID_3_GEN ((uint8_t)0b10 << 3)
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#define MR2_GOOD_DIE_BIT_PASS ((uint8_t)0b1 << 7)
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#define MR3_SRF_FAST_REFRESH ((uint8_t)0b1 << 5)
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#define MR3_OP_VOLTAGE_1V8 ((uint8_t)0b0 << 6)
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#define MR3_RBX_NOT_SUPPORTED ((uint8_t)0b0 << 7)
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#define MR4_PASR_64MB ((uint8_t)0b000 << 0)
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#define MR4_FAST_REFRESH ((uint8_t)0b0 << 3)
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#define MR4_WRITE_LATENCY_5 ((uint8_t)0b010 << 4)
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#define MR6_ULP_HALF_SLEEP ((uint8_t)0xF0 << 0)
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#define MR8_32BYTE_BURST ((uint8_t)0b01 << 0)
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#define MR8_HYBRID_BURST ((uint8_t)0b1 << 2)
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#define MR8_RBX_READ_DISABLE ((uint8_t)0b0 << 3)
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/**
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* Since the DQS line is not emulated, we have to set these values according to
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* the default configuration, which is also used by IDF
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*/
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#define OCT_PSRAM_RD_DUMMY 3
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#define OCT_PSRAM_WR_DUMMY 1
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#define FAKE_16MB_ID 0x6a
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#define FAKE_32MB_ID 0x8e
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static int get_eid_by_size(uint32_t size_mbytes) {
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switch (size_mbytes)
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{
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case 2:
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return 0x00;
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case 4:
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return 0x21;
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case 8:
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return 0x40;
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case 16:
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return FAKE_16MB_ID;
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case 32:
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return FAKE_32MB_ID;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: PSRAM size %" PRIu32 "MB not implemented\n",
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__func__, size_mbytes);
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return -1;
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}
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}
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/**
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* @brief Check if the current command is a write command
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*/
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static inline bool psram_is_write_command(SsiPsramState *s)
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{
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return s->command == WRITE || s->command == QUAD_WRITE ||
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s->command == OCT_WRITE_SYNC || s->command == OCT_WRITE_LINEAR;
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}
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/**
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* @brief Check if the current command is a read command
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*/
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static inline bool psram_is_read_command(SsiPsramState *s)
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{
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return s->command == READ || s->command == FAST_READ || s->command == FAST_READ_QUAD ||
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s->command == OCT_READ_SYNC || s->command == OCT_READ_LINEAR;
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}
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/**
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* @brief Write data to the PSRAM's internal RAM.
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* The address will be taken from the `addr` field added to the `offset`.
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*/
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static void psram_write_data(SsiPsramState *s, off_t offset, uint8_t byte)
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{
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uint8_t* ptr = (uint8_t*) memory_region_get_ram_ptr(&s->data_mr);
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const uint32_t size_bytes = s->size_mbytes * 1024 * 1024;
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off_t destination = s->addr + offset;
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if (destination < size_bytes) {
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ptr[destination] = byte;
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}
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}
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/**
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* @brief Read data from the PSRAM's internal RAM.
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* The address will be taken from the `addr` field added to the `offset`.
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*/
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static uint8_t psram_read_data(SsiPsramState *s, off_t offset)
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{
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uint8_t* ptr = (uint8_t*) memory_region_get_ram_ptr(&s->data_mr);
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const uint32_t size_bytes = s->size_mbytes * 1024 * 1024;
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off_t destination = s->addr + offset;
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if (destination < size_bytes) {
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return ptr[destination];
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}
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return 0;
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}
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static PsramState psram_quad_write_idle(SsiPsramState *s, uint32_t value)
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{
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PsramState next_state = s->state;
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/* Idle state, check if a new command is sent */
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switch (value) {
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case NOP:
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break;
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case READ_ID:
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/* Should already be 0 but let's be safe */
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s->byte_count = 0;
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next_state = ST_READ_ID;
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break;
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case WRITE:
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case QUAD_WRITE:
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case READ:
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case FAST_READ:
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case FAST_READ_QUAD:
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s->command = value;
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s->byte_count = 0;
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next_state = ST_CMD_READY;
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break;
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default:
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#if PSRAM_WARNING
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warn_report("\x1b[31m[QUAD PSRAM] Unsupported command 0x%02x \x1b[0m\n", value);
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#endif
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break;
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}
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return next_state;
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}
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/**
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* @brief Simulate a byte write on the PSRAM, returns the next state the PSRAM should be
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* put in AFTER performing the associated `read`.
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*/
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static PsramState psram_quad_write(SsiPsramState *s, uint32_t value)
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{
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/* By default, the state doens't change */
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PsramState next_state = s->state;
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switch (s->state) {
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case ST_IDLE:
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next_state = psram_quad_write_idle(s, value);
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break;
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case ST_CMD_READY:
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/* Received the (valid) command */
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s->addr = value;
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next_state = ST_CMD_ADDR0;
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break;
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case ST_CMD_ADDR0:
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s->addr = (s->addr << 8) | value;
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next_state = ST_CMD_ADDR1;
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break;
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case ST_CMD_ADDR1:
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s->addr = (s->addr << 8) | value;
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/* Only 3 bytes (24-bit) addresses on QSPI PSRAM */
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next_state = ST_PROCESSING;
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break;
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case ST_PROCESSING:
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if (psram_is_write_command(s)) {
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/* Only increment the byte_count if we are in a write command, else, the
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* `psram_quad_read` function is responsible for incrementing it */
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psram_write_data(s, s->byte_count++, value);
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}
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break;
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case ST_READ_ID:
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default:
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/* In transaction state, keep track of the number of bytes transferred */
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s->byte_count++;
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break;
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}
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return next_state;
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}
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static uint32_t psram_quad_read(SsiPsramState *s)
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{
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uint32_t result = 0;
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if (s->state == ST_READ_ID) {
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const uint8_t read_id_response[] = {
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/* 1 byte for the command itself, 3 bytes for the address */
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0x00, 0x00, 0x00, 0x00,
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PSRAM_ID_MFG, PSRAM_ID_KGD,
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get_eid_by_size(s->size_mbytes),
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0xaa, 0xbb, 0xcc, 0xdd, 0xee
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};
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const int index = s->byte_count;
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if (index < ARRAY_SIZE(read_id_response)) {
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result = read_id_response[index];
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}
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} else if (s->state == ST_PROCESSING && psram_is_read_command(s)) {
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result = psram_read_data(s, s->byte_count++);
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}
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return result;
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}
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static bool psram_octal_supported_commands(uint32_t command)
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{
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switch (command) {
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case OCT_READ_REG:
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case OCT_WRITE_REG:
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case OCT_READ_SYNC:
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case OCT_WRITE_SYNC:
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case OCT_READ_LINEAR:
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case OCT_WRITE_LINEAR:
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return true;
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default:
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return false;
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}
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}
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static uint32_t psram_octal_read(SsiPsramState *s)
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{
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uint32_t result = 0;
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if (s->state == ST_PROCESSING && s->command == OCT_READ_REG) {
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// Odd read bytes correspond to the next register
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switch (s->addr & 0xff) {
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case 0:
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result = (s->byte_count % 2) ? s->mr1 : s->mr0;
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break;
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case 1:
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result = (s->byte_count % 2) ? s->mr2 : s->mr1;
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break;
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case 2:
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result = (s->byte_count % 2) ? s->mr3 : s->mr2;
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break;
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case 3:
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result = (s->byte_count % 2) ? s->mr4 : s->mr3;
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break;
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case 4:
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result = (s->byte_count % 2) ? s->mr8 : s->mr4;
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break;
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case 8:
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result = (s->byte_count % 2) ? s->mr0 : s->mr8;
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break;
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default:
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// Should not happen
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break;
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}
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s->byte_count++;
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} else if (s->state == ST_PROCESSING && psram_is_read_command(s)) {
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result = psram_read_data(s, s->byte_count++);
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}
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return result;
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}
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static PsramState psram_octal_write(SsiPsramState *s, uint32_t value)
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{
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PsramState next_state = s->state;
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switch (s->state) {
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case ST_IDLE:
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s->command = value;
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next_state = ST_CMD_LSB;
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break;
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case ST_CMD_LSB:
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s->command |= value << 8;
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if (psram_octal_supported_commands(s->command)) {
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next_state = ST_CMD_READY;
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} else {
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#if PSRAM_WARNING
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if (s->command != 0) {
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warn_report("\x1b[31m[OCT PSRAM] Unsupported command 0x%04x \x1b[0m\n", value);
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}
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#endif
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next_state = ST_IDLE;
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}
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break;
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case ST_CMD_READY:
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/* Received the (valid) command */
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s->addr = value;
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next_state = ST_CMD_ADDR0;
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break;
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case ST_CMD_ADDR0:
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s->addr = (s->addr << 8) | value;
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next_state = ST_CMD_ADDR1;
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break;
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case ST_CMD_ADDR1:
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s->addr = (s->addr << 8) | value;
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next_state = ST_CMD_ADDR2;
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break;
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case ST_CMD_ADDR2:
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s->addr = (s->addr << 8) | value;
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/* Address was received, process data */
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/* Reading and writing registers don't introdue a dummy cycle requirement */
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if (s->command == OCT_READ_REG || psram_is_write_command(s)) {
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/* Only a single dummy byte in write mode and registers read mode */
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next_state = ST_DUMMY_CYCLE;
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s->dummy_cycles = OCT_PSRAM_WR_DUMMY;
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} else if (s->command == OCT_WRITE_REG) {
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next_state = ST_PROCESSING;
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} else {
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/* Read command */
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next_state = ST_DUMMY_CYCLE;
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s->dummy_cycles = OCT_PSRAM_RD_DUMMY;
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}
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break;
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case ST_DUMMY_CYCLE:
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s->dummy_cycles--;
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if (s->dummy_cycles == 0) {
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next_state = ST_PROCESSING;
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}
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break;
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case ST_PROCESSING:
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/* Register write only takes into account the first byte, ignores the rest */
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if (s->command == OCT_WRITE_REG && s->byte_count == 0) {
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switch (s->addr) {
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case 0:
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/* Check the latency bits */
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if (MR0_GET_RD_LATENCY(value) != 2) {
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warn_report("\x1b[31m[OCT PSRAM] Read Latency %d unsupported\x1b[0m\n", MR0_GET_RD_LATENCY(value));
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}
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s->mr0 = value;
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break;
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case 4:
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s->mr4 = value;
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break;
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case 8:
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s->mr8 = value;
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break;
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}
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s->byte_count++;
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} else if (psram_is_write_command(s)) {
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/* Only increment the byte_count if we are in a write command, else, the
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* `read` function is responsible for incrementing it */
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psram_write_data(s, s->byte_count++, value);
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}
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break;
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default:
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break;
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}
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return next_state;
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}
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static int psram_octal_get_density(uint32_t size_mbytes)
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{
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int density = 0;
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/* These density values were taken from ESP-IDF Octal PSRAM driver */
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switch (size_mbytes) {
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case 4:
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density = 1;
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break;
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case 8:
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density = 3;
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break;
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case 16:
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density = 5;
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break;
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case 32:
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density = 7;
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break;
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case 64:
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density = 6;
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break;
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default:
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error_report("[PSRAM] Invalid size %dMB for octal PSRAM\n", size_mbytes);
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break;
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}
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return density & MR2_DENSITY_MASK;
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}
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static uint32_t psram_transfer(SSIPeripheral *dev, uint32_t value)
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{
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SsiPsramState *s = SSI_PSRAM(dev);
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PsramState next_state;
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uint32_t data;
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if (s->is_octal) {
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next_state = psram_octal_write(s, value);
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data = psram_octal_read(s);
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} else {
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next_state = psram_quad_write(s, value);
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data = psram_quad_read(s);
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}
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/* Set the new state AFTER calling read */
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s->state = next_state;
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return data;
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}
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static int psram_cs(SSIPeripheral *ss, bool select)
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{
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SsiPsramState *s = SSI_PSRAM(ss);
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if (!select) {
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/* If data were written to the cache via the MemoryRegion, we need to
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* mark the area as dirty since the ESP target's `cache` also uses it. */
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if (s->state == ST_PROCESSING && psram_is_write_command(s)) {
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memory_region_set_dirty(&s->data_mr, s->addr, s->byte_count);
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}
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s->state = ST_IDLE;
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s->byte_count = 0;
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s->command = -1;
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s->addr = -1;
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s->dummy_cycles = 0;
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}
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return 0;
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}
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static void psram_realize(SSIPeripheral *ss, Error **errp)
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{
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SsiPsramState *s = SSI_PSRAM(ss);
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if (s->is_octal) {
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/* Set the default MR values for the octal psram (ref: Datasheet APS6408L_OBMx) */
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s->mr0 = MR0_RD_LT_VARIABLE | MR0_RD_LATENCY_CODE | MR0_DRIVE_STRENGHT_HALF;
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s->mr1 = MR1_NO_ULP | MR1_VENDOR_ID;
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s->mr2 = MR2_GOOD_DIE_BIT_PASS | MR2_DEVICE_ID_3_GEN | psram_octal_get_density(s->size_mbytes);
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s->mr3 = MR3_RBX_NOT_SUPPORTED | MR3_OP_VOLTAGE_1V8 | MR3_SRF_FAST_REFRESH;
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s->mr4 = MR4_WRITE_LATENCY_5 | MR4_FAST_REFRESH | MR4_PASR_64MB;
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s->mr8 = MR8_RBX_READ_DISABLE | MR8_HYBRID_BURST | MR8_32BYTE_BURST;
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} else if (get_eid_by_size(s->size_mbytes) == -1) {
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error_report("[PSRAM] Invalid size %dMB for QUAD PSRAM", s->size_mbytes);
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}
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/* Allocate the actual array that will act as a vritual RAM */
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const uint32_t size_bytes = s->size_mbytes * 1024 * 1024;
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memory_region_init_ram(&s->data_mr, OBJECT(s), "psram.memory_region", size_bytes, &error_fatal);
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s->state = ST_IDLE;
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}
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static Property psram_properties[] = {
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DEFINE_PROP_BOOL("is_octal", SsiPsramState, is_octal, false),
|
|
DEFINE_PROP_UINT32("size_mbytes", SsiPsramState, size_mbytes, 4),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
|
|
static void psram_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
k->transfer = psram_transfer;
|
|
k->set_cs = psram_cs;
|
|
k->cs_polarity = SSI_CS_LOW;
|
|
k->realize = psram_realize;
|
|
device_class_set_props(dc, psram_properties);
|
|
}
|
|
|
|
static const TypeInfo psram_info = {
|
|
.name = TYPE_SSI_PSRAM,
|
|
.parent = TYPE_SSI_PERIPHERAL,
|
|
.instance_size = sizeof(SsiPsramState),
|
|
.class_init = psram_class_init
|
|
};
|
|
|
|
static void psram_register_types(void)
|
|
{
|
|
type_register_static(&psram_info);
|
|
}
|
|
|
|
type_init(psram_register_types)
|