Omar Chebib
309 lines
9.5 KiB
C
309 lines
9.5 KiB
C
/*
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* ESP32 eFuse emulation
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*
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* Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "sysemu/sysemu.h"
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#include "chardev/char-fe.h"
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#include "hw/registerfields.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/nvram/esp32_efuse.h"
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static void esp32_efuse_read_op(Esp32EfuseState *s);
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static void esp32_efuse_program_op(Esp32EfuseState *s);
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static void esp32_efuse_update_irq(Esp32EfuseState *s);
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static void esp32_efuse_op_timer_start(Esp32EfuseState *s);
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static uint64_t esp32_efuse_read(void *opaque, hwaddr addr, unsigned int size)
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{
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Esp32EfuseState *s = ESP32_EFUSE(opaque);
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uint64_t r = 0;
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int idx;
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switch (addr) {
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case A_EFUSE_BLK0_RDATA0 ... A_EFUSE_BLK0_WDATA0 - 4:
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idx = (addr - A_EFUSE_BLK0_RDATA0) / 4;
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r = s->efuse_rd.blk0[idx] & ~(s->efuse_rd_dis.blk0[idx]);
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break;
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case A_EFUSE_BLK0_WDATA0 ... A_EFUSE_BLK1_RDATA0 - 4:
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r = s->efuse_wr.blk0[(addr - A_EFUSE_BLK0_WDATA0) / 4];
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break;
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case A_EFUSE_BLK1_RDATA0 ... A_EFUSE_BLK2_RDATA0 - 4:
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idx = (addr - A_EFUSE_BLK1_RDATA0) / 4;
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r = s->efuse_rd.blk1[idx] & ~(s->efuse_rd_dis.blk1[idx]);
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break;
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case A_EFUSE_BLK2_RDATA0 ... A_EFUSE_BLK3_RDATA0 - 4:
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idx = (addr - A_EFUSE_BLK2_RDATA0) / 4;
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r = s->efuse_rd.blk2[idx] & ~(s->efuse_rd_dis.blk2[idx]);
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break;
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case A_EFUSE_BLK3_RDATA0 ... A_EFUSE_BLK1_WDATA0 - 4:
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idx = (addr - A_EFUSE_BLK3_RDATA0) / 4;
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r = s->efuse_rd.blk3[idx] & ~(s->efuse_rd_dis.blk3[idx]);
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break;
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case A_EFUSE_BLK1_WDATA0 ... A_EFUSE_BLK2_WDATA0 - 4:
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r = s->efuse_wr.blk1[(addr - A_EFUSE_BLK1_WDATA0) / 4];
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break;
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case A_EFUSE_BLK2_WDATA0 ... A_EFUSE_BLK3_WDATA0 - 4:
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r = s->efuse_wr.blk2[(addr - A_EFUSE_BLK2_WDATA0) / 4];
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break;
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case A_EFUSE_BLK3_WDATA0 ... A_EFUSE_CLK - 4:
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r = s->efuse_wr.blk3[(addr - A_EFUSE_BLK3_WDATA0) / 4];
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break;
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case A_EFUSE_CLK:
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r = s->clk_reg;
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break;
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case A_EFUSE_CONF:
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r = s->conf_reg;
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break;
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case A_EFUSE_CMD:
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r = s->cmd_reg;
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break;
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case A_EFUSE_STATUS:
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r = 0;
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break;
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case A_EFUSE_DAC_CONF:
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r = s->dac_conf_reg;
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break;
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case A_EFUSE_INT_RAW:
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r = s->int_raw_reg;
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break;
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case A_EFUSE_INT_ST:
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r = s->int_st_reg;
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break;
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case A_EFUSE_INT_ENA:
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r = s->int_ena_reg;
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break;
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case A_EFUSE_DEC_STATUS:
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r = 0;
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break;
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case A_EFUSE_DATE:
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r = 0x16042600;
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}
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return r;
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}
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static void esp32_efuse_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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Esp32EfuseState *s = ESP32_EFUSE(opaque);
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switch (addr) {
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case A_EFUSE_CLK:
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s->clk_reg = value;
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break;
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case A_EFUSE_CONF:
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s->conf_reg = value;
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break;
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case A_EFUSE_CMD:
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if ((value & EFUSE_READ) && s->conf_reg == EFUSE_READ_OP_CODE) {
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esp32_efuse_read_op(s);
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}
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if ((value & EFUSE_PGM) && s->conf_reg == EFUSE_PGM_OP_CODE) {
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esp32_efuse_program_op(s);
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}
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break;
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case A_EFUSE_DAC_CONF:
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s->dac_conf_reg = value;
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break;
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case A_EFUSE_INT_ENA:
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s->int_ena_reg = value;
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esp32_efuse_update_irq(s);
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break;
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case A_EFUSE_INT_CLR:
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s->int_raw_reg &= ~value;
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esp32_efuse_update_irq(s);
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break;
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case A_EFUSE_BLK0_WDATA0 ... A_EFUSE_BLK1_RDATA0 - 4:
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s->efuse_wr.blk0[(addr - A_EFUSE_BLK0_WDATA0) / 4] = value;
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break;
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case A_EFUSE_BLK1_WDATA0 ... A_EFUSE_BLK2_WDATA0 - 4:
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s->efuse_wr.blk1[(addr - A_EFUSE_BLK1_WDATA0) / 4] = value;
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break;
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case A_EFUSE_BLK2_WDATA0 ... A_EFUSE_BLK3_WDATA0 - 4:
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s->efuse_wr.blk2[(addr - A_EFUSE_BLK2_WDATA0) / 4] = value;
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break;
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case A_EFUSE_BLK3_WDATA0 ... A_EFUSE_CLK - 4:
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s->efuse_wr.blk3[(addr - A_EFUSE_BLK3_WDATA0) / 4] = value;
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break;
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}
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}
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#define APPLY_DIS(rdwr_, ctrl_field_, dest_field_) \
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if (s->efuse_ ## rdwr_ .blk0_d0.ctrl_field_) { \
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memset(&s->efuse_ ## rdwr_ ## _dis.dest_field_, 0xff, sizeof(s->efuse_ ## rdwr_ ## _dis.dest_field_)); \
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}
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#define APPLY_DIS_FIELD(rdwr_, ctrl_field_, dest_field_) \
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if (s->efuse_ ## rdwr_ .blk0_d0.ctrl_field_) { \
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s->efuse_ ## rdwr_ ## _dis.dest_field_ = 0; \
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s->efuse_ ## rdwr_ ## _dis.dest_field_ -= 1; \
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}
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static void esp32_efuse_read_op(Esp32EfuseState *s)
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{
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s->cmd_reg = EFUSE_READ;
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if (s->blk != NULL) {
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int ret = blk_pread(s->blk, 0, sizeof(s->efuse_rd), &s->efuse_rd, 0);
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if (ret < 0) {
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error_report("%s: failed to read the block device (%d)", __func__, ret);
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return;
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}
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}
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memset(&s->efuse_rd_dis, 0, sizeof(s->efuse_rd_dis));
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memset(&s->efuse_wr_dis, 0, sizeof(s->efuse_wr_dis));
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APPLY_DIS(rd, rd_dis_blk1, blk1);
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APPLY_DIS(rd, rd_dis_blk2, blk2);
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APPLY_DIS(rd, rd_dis_blk3, blk3);
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APPLY_DIS_FIELD(rd, rd_dis_blk0_partial, blk0_d5.flash_crypt_config);
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APPLY_DIS_FIELD(rd, rd_dis_blk0_partial, blk0_d6.coding_scheme);
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APPLY_DIS_FIELD(rd, rd_dis_blk0_partial, blk0_d6.key_status);
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APPLY_DIS(wr, wr_dis_blk1, blk1);
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APPLY_DIS(wr, wr_dis_blk2, blk2);
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APPLY_DIS(wr, wr_dis_blk3, blk3);
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/* Other wr_dis bits are not emulated, but can be handled here if necessary */
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esp32_efuse_op_timer_start(s);
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qemu_irq_pulse(s->efuse_update_gpio);
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}
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static void esp32_efuse_program_op(Esp32EfuseState *s)
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{
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s->cmd_reg = EFUSE_PGM;
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Esp32EfuseRegs result;
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uint32_t* dst = (uint32_t*) &result;
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uint32_t* rd = (uint32_t*) &s->efuse_rd;
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uint32_t* wr = (uint32_t*) &s->efuse_wr;
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uint32_t* wr_dis = (uint32_t*) &s->efuse_wr_dis;
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for (int i = 0; i < sizeof(result) / sizeof(uint32_t); ++i) {
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uint32_t wr_word = wr[i];
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uint32_t wr_dis_word = wr_dis[i];
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uint32_t rd_word = rd[i];
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dst[i] = (wr_word & (~wr_dis_word)) | rd_word;
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}
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if (s->blk != NULL) {
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int ret = blk_pwrite(s->blk, 0, sizeof(result), &result, 0);
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if (ret < 0) {
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error_report("%s: failed to write to block device (%d)", __func__, ret);
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}
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}
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esp32_efuse_op_timer_start(s);
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}
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static void esp32_efuse_update_irq(Esp32EfuseState *s)
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{
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s->int_st_reg = s->int_ena_reg & s->int_raw_reg;
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int level = s->int_st_reg != 0;
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qemu_set_irq(s->irq, level);
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}
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static void esp32_efuse_op_timer_start(Esp32EfuseState *s)
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{
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uint64_t ns_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t interval_ns = 100000000; /* 10 ms, make this depend on EFUSE_CLK register */
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timer_mod_anticipate_ns(&s->op_timer, ns_now + interval_ns);
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}
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static void esp32_efuse_timer_cb(void *opaque)
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{
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Esp32EfuseState *s = ESP32_EFUSE(opaque);
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uint32_t cmd = s->cmd_reg;
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s->cmd_reg = 0;
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s->int_raw_reg |= cmd;
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esp32_efuse_update_irq(s);
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}
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static const MemoryRegionOps esp32_efuse_ops = {
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.read = esp32_efuse_read,
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.write = esp32_efuse_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void esp32_efuse_reset_hold(Object *obj, ResetType type)
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{
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Esp32EfuseState *s = ESP32_EFUSE(obj);
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esp32_efuse_read_op(s);
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}
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static void esp32_efuse_realize(DeviceState *dev, Error **errp)
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{
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Esp32EfuseState *s = ESP32_EFUSE(dev);
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if (s->blk != NULL) {
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if (!blk_supports_write_perm(s->blk)) {
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error_setg(errp, "%s: block device is not writeable", __func__);
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return;
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}
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uint64_t perm = BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE;
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int ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, NULL);
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if (ret != 0) {
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error_setg(errp, "%s: failed to set permission (%d)", __func__, ret);
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return;
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}
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}
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}
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static void esp32_efuse_init(Object *obj)
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{
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Esp32EfuseState *s = ESP32_EFUSE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &esp32_efuse_ops, s,
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TYPE_ESP32_EFUSE, A_EFUSE_DATE + 4);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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timer_init_ns(&s->op_timer, QEMU_CLOCK_VIRTUAL, esp32_efuse_timer_cb, s);
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qdev_init_gpio_out_named(DEVICE(sbd), &s->efuse_update_gpio, ESP32_EFUSE_UPDATE_GPIO, 1);
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memset(&s->efuse_rd, 0, sizeof(s->efuse_rd));
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memset(&s->efuse_wr, 0, sizeof(s->efuse_wr));
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}
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static Property esp32_efuse_properties[] = {
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DEFINE_PROP_DRIVE("drive", Esp32EfuseState, blk),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void esp32_efuse_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.hold = esp32_efuse_reset_hold;
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dc->realize = esp32_efuse_realize;
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device_class_set_props(dc, esp32_efuse_properties);
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}
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static const TypeInfo esp32_efuse_info = {
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.name = TYPE_ESP32_EFUSE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Esp32EfuseState),
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.instance_init = esp32_efuse_init,
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.class_init = esp32_efuse_class_init
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};
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static void esp32_efuse_register_types(void)
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{
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type_register_static(&esp32_efuse_info);
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}
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type_init(esp32_efuse_register_types)
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