hw/nvram: implement ESP32-C3 eFuses

hw/nvram/esp32c3_efuse.c

@@ -0,0 +1,69 @@
+/*
+ * ESP32-C3 eFuse emulation
+ *
+ * Copyright (c) 2023-2024 Espressif Systems (Shanghai) Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nvram/esp32c3_efuse.h"
+
+
+static void esp32c3_efuse_realize(DeviceState *dev, Error **errp)
+{
+    ESP32C3EfuseClass* esp32c3_class = ESP32C3_EFUSE_GET_CLASS(dev);
+    ESPEfuseState *s = ESP_EFUSE(dev);
+
+    /* Call the realize function of the parent class, which will initialize the efuse blocks
+     * or the efuse mirror (in RAM) */
+    esp32c3_class->parent_realize(dev, errp);
+
+    /* If no file was given as efuses, create a temporary one (in RAM). */
+    if (s->blk == NULL) {
+        assert(s->mirror != NULL);
+
+        /* Set the chip revision to v0.3 and write it to the file */
+        s->efuses.blocks.rd_mac_spi_sys_3 = FIELD_DP32(0, EFUSE_RD_MAC_SPI_SYS_3, WAFER_VER_MINOR_LO, 3);
+
+        /* Set the chip eFuse block revision 1.3 */
+        s->efuses.blocks.rd_sys_part1_data4 = FIELD_DP32(0, EFUSE_RD_SYS_PART1_DATA4, BLK_VERSION_MAJOR, 1);
+        s->efuses.blocks.rd_mac_spi_sys_3 = FIELD_DP32(s->efuses.blocks.rd_mac_spi_sys_3,
+                                                       EFUSE_RD_MAC_SPI_SYS_3, BLK_VERSION_MINOR, 3);
+
+        memcpy(s->mirror, &s->efuses.blocks, sizeof(ESPEfuseBlocks));
+    }
+}
+
+
+static void esp32c3_efuse_init(Object *obj)
+{
+    /* No need to call parent's class function, this is done automatically by the QOM, even before
+     * calling the current function. */
+}
+
+static void esp32c3_efuse_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ESP32C3EfuseClass* esp32c3_efuse = ESP32C3_EFUSE_CLASS(klass);
+
+    device_class_set_parent_realize(dc, esp32c3_efuse_realize, &esp32c3_efuse->parent_realize);
+}
+
+static const TypeInfo esp32c3_efuse_info = {
+    .name = TYPE_ESP32C3_EFUSE,
+    .parent = TYPE_ESP_EFUSE,
+    .instance_size = sizeof(ESP32C3EfuseState),
+    .instance_init = esp32c3_efuse_init,
+    .class_init = esp32c3_efuse_class_init,
+    .class_size = sizeof(ESP32C3EfuseClass)
+};
+
+static void esp32c3_efuse_register_types(void)
+{
+    type_register_static(&esp32c3_efuse_info);
+}
+
+type_init(esp32c3_efuse_register_types)

hw/nvram/meson.build

@@ -9,6 +9,7 @@ system_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
 system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
 system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
 system_ss.add(when: 'CONFIG_XTENSA_ESP32', if_true: files('esp32_efuse.c'))
+system_ss.add(when: 'CONFIG_RISCV_ESP32C3', if_true: files('esp32c3_efuse.c', 'esp_efuse.c'))
 system_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
 system_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
 system_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(

include/hw/nvram/esp32c3_efuse.h

@@ -0,0 +1,37 @@
+/*
+ * ESP32-C3 eFuse emulation
+ *
+ * Copyright (c) 2023-2024 Espressif Systems (Shanghai) Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+#pragma once
+
+#include "esp_efuse.h"
+
+#define TYPE_ESP32C3_EFUSE "nvram.esp32c3.efuse"
+#define ESP32C3_EFUSE(obj) OBJECT_CHECK(ESP32C3EfuseState, (obj), TYPE_ESP32C3_EFUSE)
+#define ESP32C3_EFUSE_GET_CLASS(obj) OBJECT_GET_CLASS(ESP32C3EfuseClass, obj, TYPE_ESP32C3_EFUSE)
+#define ESP32C3_EFUSE_CLASS(klass) OBJECT_CLASS_CHECK(ESP32C3EfuseClass, klass, TYPE_ESP32C3_EFUSE)
+
+
+typedef struct ESP32C3EfuseState {
+    ESPEfuseState parent;
+} ESP32C3EfuseState;
+
+
+typedef struct ESP32C3EfuseClass {
+    ESPEfuseClass parent_class;
+    DeviceRealize parent_realize;
+} ESP32C3EfuseClass;
+
+
+/* These registers only need to be initialized for the C3 target */
+REG32(EFUSE_RD_MAC_SPI_SYS_3, 0x50)
+    FIELD(EFUSE_RD_MAC_SPI_SYS_3, BLK_VERSION_MINOR, 24, 3)
+    FIELD(EFUSE_RD_MAC_SPI_SYS_3, WAFER_VER_MINOR_LO, 18, 3)
+
+REG32(EFUSE_RD_SYS_PART1_DATA4, 0x6C)
+    FIELD(EFUSE_RD_SYS_PART1_DATA4, BLK_VERSION_MAJOR, 0, 2)