feat(xtensa/esp32s3): Extend the ESP32-S3's TIE instructions
1. Missing bare ee.vldbc.{8,16,32} instructions - Added 3 opcode table entries with addr_nop and updated translate_vldbc_s3 to handle addr_nop without erroring.
2. Missing ee.st.qacc_{h,l}.{h.32,l.128}.ip store instructions - Added 4 opcode table entries, 2 translate functions, and 2 helper functions (with declarations in helper.h) to implement the QACC store operations as mirrors of the existing load counterparts.
3. ee.src.q incorrect qs1->qs0 copy - The bare ee.src.q qa, qs0, qs1 was incorrectly copying qs1→qs0 after the funnel shift. Per the TRM, only the .qup variant does this copy. Fixed by making the copy conditional on op_type == vmul_qup.
4. Add ee.st.accx.ip to store 40-bit ACCX (zero-extended to 64-bit) to memory, 8-byte aligned.
5. Add ee.ld.ua_state.ip to load 128-bit UA_STATE from memory, 16-byte aligned.
6. Add ee.st.ua_state.ip to store 128-bit UA_STATE to memory, 16-byte aligned.
7. Add ee.ldxq.32: Indexed load: compute address from Q register s16 segment, load 32-bit into Q register segment.
8. Add ee.stxq.32: Indexed store: compute address from Q register s16 segment, store 32-bit from Q register segment.
This commit is contained in:
harshal.patil
committed by
Ivan Grokhotkov
Ivan Grokhotkov
parent
a06102167d
commit
ba5950398f
@@ -178,8 +178,19 @@ DEF_HELPER_4(wr_mask_gpio_out_s3, i32, env, i32, i32, i32)
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DEF_HELPER_3(mv_qr_s3, void, env, i32, i32)
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DEF_HELPER_2(ld_accx_s3, void, env, i64)
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DEF_HELPER_1(st_accx_s3, i64, env)
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DEF_HELPER_2(srs_accx_s3, i32, env, i32)
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DEF_HELPER_3(ld_ua_state_s3, void, env, i64, i32)
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DEF_HELPER_2(st_ua_state_s3, i64, env, i32)
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DEF_HELPER_4(ldxq_32_s3, void, env, i32, i32, i32)
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DEF_HELPER_3(stxq_32_s3, i32, env, i32, i32)
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DEF_HELPER_3(ldstxq_addr_s3, i32, env, i32, i32)
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DEF_HELPER_3(ld_qacc_x_h_32_ip_s3, void, env, i32, i32)
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DEF_HELPER_2(st_qacc_x_h_32_ip_s3, i32, env, i32)
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DEF_HELPER_4(ld_qacc_x_l_128_ip_s3, void, env, i32, i32, i64)
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DEF_HELPER_3(st_qacc_x_l_128_ip_s3, i64, env, i32, i32)
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@@ -692,7 +692,7 @@ static void translate_vldbc_s3(DisasContext *dc, const OpcodeArg arg[], const ui
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{
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if (vldbc_8 == par[1]) tcg_gen_addi_i32(arg[1].out, arg[1].in, 1);
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if (vldbc_16 == par[1]) tcg_gen_addi_i32(arg[1].out, arg[1].in, 2);
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} else
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} else if (par[0] != addr_nop)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "unknown instruction extension (pc = %08x)\n", dc->pc);
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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@@ -2846,17 +2846,26 @@ void HELPER(src_q_s3)(CPUXtensaState *env, uint32_t qa, uint32_t qs0, uint32_t q
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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int sar_value = tie->SAR_BYTE;
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/* Need a temp copy since qa may alias qs0 or qs1 */
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Q_reg tmp;
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for (int i = 0; i < (16 - sar_value); i++)
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{
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tie->Q[qa].u8[i] = tie->Q[qs0].u8[i + sar_value];
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tmp.u8[i] = tie->Q[qs0].u8[i + sar_value];
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}
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for (int i = 0; i < sar_value; i++)
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{
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tie->Q[qa].u8[16 - sar_value + i] = tie->Q[qs1].u8[i];
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tmp.u8[16 - sar_value + i] = tie->Q[qs1].u8[i];
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}
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for (int i = 0; i < 16; i++)
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tie->Q[qa].u64[0] = tmp.u64[0];
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tie->Q[qa].u64[1] = tmp.u64[1];
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/* QUP variant: also copy qs1 → qs0 */
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if (op_type == vmul_qup)
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{
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tie->Q[qs0].u8[i] = tie->Q[qs1].u8[i];
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for (int i = 0; i < 16; i++)
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{
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tie->Q[qs0].u8[i] = tie->Q[qs1].u8[i];
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}
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}
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}
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@@ -3967,6 +3976,92 @@ void HELPER(ld_qacc_x_l_128_ip_s3)(CPUXtensaState *env, uint32_t op_type, uint32
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}
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}
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/* Store upper 32 bits of QACC_H or QACC_L to memory */
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uint32_t HELPER(st_qacc_x_h_32_ip_s3)(CPUXtensaState *env, uint32_t op_type)
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{
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ACCQ_reg *qacc = cpu_qacc_ptr(env, 1);
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if (op_type == wrur_qacc_l_0)
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{
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qacc = cpu_qacc_ptr(env, 0);
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}
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uint32_t data;
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uint8_t* data_ptr = (uint8_t*)&data;
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data_ptr[0] = qacc->u8[16];
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data_ptr[1] = qacc->u8[17];
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data_ptr[2] = qacc->u8[18];
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data_ptr[3] = qacc->u8[19];
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return data;
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}
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/* Store lower 128 bits of QACC_H or QACC_L to memory (64-bit chunk) */
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uint64_t HELPER(st_qacc_x_l_128_ip_s3)(CPUXtensaState *env, uint32_t op_type, uint32_t index)
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{
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ACCQ_reg *qacc = cpu_qacc_ptr(env, 1);
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if (op_type == wrur_qacc_l_0)
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{
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qacc = cpu_qacc_ptr(env, 0);
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}
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uint64_t data;
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uint8_t* data_ptr = (uint8_t*)&data;
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for (int i = 0; i < 8; i++)
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{
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data_ptr[i] = qacc->u8[i + index * 8];
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}
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return data;
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}
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static void translate_st_qacc_x_h_32_ip_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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TCGv_i32 op_type = tcg_constant_i32((uint32_t)par[0]);
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TCGv_i32 addr = tcg_temp_new_i32();
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// Align to 32 bit
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tcg_gen_andi_i32(addr, arg[0].in, 0xfffffffc);
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MemOp mop = gen_load_store_alignment(dc, MO_32 | MO_TE, addr);
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TCGv_i32 data = tcg_temp_new_i32();
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gen_helper_st_qacc_x_h_32_ip_s3(data, tcg_env, op_type);
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tcg_gen_qemu_st_i32(data, addr, dc->cring, mop);
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tcg_gen_addi_i32(arg[0].out, arg[0].in, arg[1].imm);
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tcg_temp_free_i32(data);
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(op_type);
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}
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static void translate_st_qacc_x_l_128_ip_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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TCGv_i32 op_type = tcg_constant_i32((uint32_t)par[0]);
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for (int i = 0; i < 2; i++)
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{
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TCGv_i32 addr;
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MemOp mop;
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addr = tcg_temp_new_i32();
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// Align to 128 bit
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tcg_gen_andi_i32(addr, arg[0].in, 0xfffffff0);
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tcg_gen_addi_i32(addr, addr, i * 8);
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mop = gen_load_store_alignment(dc, MO_64 | MO_TE, addr);
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TCGv_i64 data = tcg_temp_new_i64();
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TCGv_i32 index = tcg_constant_i32(i);
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gen_helper_st_qacc_x_l_128_ip_s3(data, tcg_env, op_type, index);
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tcg_gen_qemu_st_i64(data, addr, dc->cring, mop);
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tcg_temp_free_i64(data);
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(index);
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}
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tcg_gen_addi_i32(arg[0].out, arg[0].in, arg[1].imm);
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tcg_temp_free_i32(op_type);
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}
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static void translate_ld_qacc_x_l_128_ip_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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TCGv_i32 op_type = tcg_constant_i32((uint32_t)par[0]);
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@@ -3999,6 +4094,188 @@ static void translate_ld_qacc_x_l_128_ip_s3(DisasContext *dc, const OpcodeArg ar
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tcg_temp_free_i32(op_type);
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}
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/* EE.ST.ACCX.IP: store ACCX (40-bit, zero-extended to 64-bit) to memory */
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uint64_t HELPER(st_accx_s3)(CPUXtensaState *env)
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{
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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return (uint64_t)(tie->ACCX & 0x000000ffffffffffULL);
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}
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static void translate_st_accx_ip_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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TCGv_i32 addr = tcg_temp_new_i32();
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/* Align to 8 bytes */
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tcg_gen_andi_i32(addr, arg[0].in, 0xfffffff8);
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MemOp mop = gen_load_store_alignment(dc, MO_64 | MO_TE, addr);
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TCGv_i64 data = tcg_temp_new_i64();
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gen_helper_st_accx_s3(data, tcg_env);
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tcg_gen_qemu_st_i64(data, addr, dc->cring, mop);
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tcg_gen_addi_i32(arg[0].out, arg[0].in, arg[1].imm);
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tcg_temp_free_i64(data);
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tcg_temp_free_i32(addr);
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}
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/* EE.LD.UA_STATE.IP: load 128-bit UA_STATE from memory */
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void HELPER(ld_ua_state_s3)(CPUXtensaState *env, uint64_t data, uint32_t low_high)
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{
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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tie->UA_STATE.u64[low_high] = data;
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}
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static void translate_ld_ua_state_ip_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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for (int i = 0; i < 2; i++)
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{
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TCGv_i32 addr = tcg_temp_new_i32();
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/* Align to 16 bytes */
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tcg_gen_andi_i32(addr, arg[0].in, 0xfffffff0);
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tcg_gen_addi_i32(addr, addr, i * 8);
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MemOp mop = gen_load_store_alignment(dc, MO_64 | MO_TE, addr);
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TCGv_i64 data = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(data, addr, dc->cring, mop);
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TCGv_i32 low_high = tcg_constant_i32(i);
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gen_helper_ld_ua_state_s3(tcg_env, data, low_high);
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tcg_temp_free_i64(data);
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(low_high);
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}
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tcg_gen_addi_i32(arg[0].out, arg[0].in, arg[1].imm);
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}
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/* EE.ST.UA_STATE.IP: store 128-bit UA_STATE to memory */
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uint64_t HELPER(st_ua_state_s3)(CPUXtensaState *env, uint32_t low_high)
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{
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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return tie->UA_STATE.u64[low_high];
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}
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static void translate_st_ua_state_ip_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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for (int i = 0; i < 2; i++)
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{
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TCGv_i32 addr = tcg_temp_new_i32();
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/* Align to 16 bytes */
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tcg_gen_andi_i32(addr, arg[0].in, 0xfffffff0);
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tcg_gen_addi_i32(addr, addr, i * 8);
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MemOp mop = gen_load_store_alignment(dc, MO_64 | MO_TE, addr);
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TCGv_i64 data = tcg_temp_new_i64();
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TCGv_i32 low_high = tcg_constant_i32(i);
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gen_helper_st_ua_state_s3(data, tcg_env, low_high);
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tcg_gen_qemu_st_i64(data, addr, dc->cring, mop);
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tcg_temp_free_i64(data);
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(low_high);
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}
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tcg_gen_addi_i32(arg[0].out, arg[0].in, arg[1].imm);
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}
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/* EE.LDXQ.32: indexed load 32-bit into Q register segment */
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void HELPER(ldxq_32_s3)(CPUXtensaState *env, uint32_t qu, uint32_t sel4, uint32_t data)
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{
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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tie->Q[qu].u32[sel4] = data;
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}
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static void translate_ldxq_32_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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/* EE.LDXQ.32 qu, qs, as, sel4, sel8 */
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/* arg[0]=qu, arg[1]=qs, arg[2]=as, arg[3]=sel4(imm), arg[4]=sel8(imm) */
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uint32_t sel8 = (uint32_t)arg[4].imm;
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uint32_t sel4 = (uint32_t)arg[3].imm;
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/* Compute address: as + sign_extend(qs.s16[sel8]) * 4 - 4, aligned to 4 */
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TCGv_i32 qs_idx = tcg_constant_i32((uint32_t)arg[1].imm);
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TCGv_i32 sel8_val = tcg_constant_i32(sel8);
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TCGv_i32 offset = tcg_temp_new_i32();
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gen_helper_ldstxq_addr_s3(offset, tcg_env, qs_idx, sel8_val);
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TCGv_i32 addr = tcg_temp_new_i32();
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tcg_gen_add_i32(addr, arg[2].in, offset);
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tcg_gen_andi_i32(addr, addr, 0xfffffffc);
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MemOp mop = gen_load_store_alignment(dc, MO_32 | MO_TE, addr);
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TCGv_i32 data = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(data, addr, dc->cring, mop);
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TCGv_i32 qu_idx = tcg_constant_i32((uint32_t)arg[0].imm);
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TCGv_i32 sel4_val = tcg_constant_i32(sel4);
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gen_helper_ldxq_32_s3(tcg_env, qu_idx, sel4_val, data);
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tcg_temp_free_i32(data);
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(offset);
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tcg_temp_free_i32(qs_idx);
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tcg_temp_free_i32(sel8_val);
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tcg_temp_free_i32(qu_idx);
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tcg_temp_free_i32(sel4_val);
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}
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/* EE.STXQ.32: indexed store 32-bit from Q register segment */
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uint32_t HELPER(stxq_32_s3)(CPUXtensaState *env, uint32_t qv, uint32_t sel4)
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{
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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return tie->Q[qv].u32[sel4];
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}
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/* Helper to compute address offset: sign_extend(qs.s16[sel8]) * 4 - 4 */
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uint32_t HELPER(ldstxq_addr_s3)(CPUXtensaState *env, uint32_t qs, uint32_t sel8)
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{
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CPUXtensaEsp32s3State* tie = (CPUXtensaEsp32s3State*)(env->ext);
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int32_t offset = (int32_t)tie->Q[qs].s16[sel8];
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return offset * 4 - 4;
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}
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static void translate_stxq_32_s3(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[])
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{
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/* EE.STXQ.32 qv, qs, as, sel4, sel8 */
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/* arg[0]=qv, arg[1]=qs, arg[2]=as, arg[3]=sel4(imm), arg[4]=sel8(imm) */
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uint32_t sel8 = (uint32_t)arg[4].imm;
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uint32_t sel4 = (uint32_t)arg[3].imm;
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/* Get data to store */
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TCGv_i32 qv_idx = tcg_constant_i32((uint32_t)arg[0].imm);
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TCGv_i32 sel4_val = tcg_constant_i32(sel4);
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TCGv_i32 data = tcg_temp_new_i32();
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gen_helper_stxq_32_s3(data, tcg_env, qv_idx, sel4_val);
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/* Compute address: as + sign_extend(qs.s16[sel8]) * 4 - 4, aligned to 4 */
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TCGv_i32 qs_idx = tcg_constant_i32((uint32_t)arg[1].imm);
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TCGv_i32 sel8_val = tcg_constant_i32(sel8);
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TCGv_i32 offset = tcg_temp_new_i32();
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gen_helper_ldstxq_addr_s3(offset, tcg_env, qs_idx, sel8_val);
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TCGv_i32 addr = tcg_temp_new_i32();
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tcg_gen_add_i32(addr, arg[2].in, offset);
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tcg_gen_andi_i32(addr, addr, 0xfffffffc);
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MemOp mop = gen_load_store_alignment(dc, MO_32 | MO_TE, addr);
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tcg_gen_qemu_st_i32(data, addr, dc->cring, mop);
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tcg_temp_free_i32(data);
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(offset);
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tcg_temp_free_i32(qv_idx);
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tcg_temp_free_i32(sel4_val);
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tcg_temp_free_i32(qs_idx);
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tcg_temp_free_i32(sel8_val);
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}
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static const XtensaOpcodeOps tie_ops[] = {
|
||||
// VLD.L/H.64.ip/xp
|
||||
{
|
||||
@@ -4116,7 +4393,29 @@ static const XtensaOpcodeOps tie_ops[] = {
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
// VLDBC 8/16/32 bit
|
||||
// VLDBC 8/16/32 bit (bare, no address update)
|
||||
{
|
||||
.name = "ee.vldbc.8",
|
||||
.translate = translate_vldbc_s3,
|
||||
.par = (const uint32_t[]){addr_nop, vldbc_8},
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.vldbc.16",
|
||||
.translate = translate_vldbc_s3,
|
||||
.par = (const uint32_t[]){addr_nop, vldbc_16},
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.vldbc.32",
|
||||
.translate = translate_vldbc_s3,
|
||||
.par = (const uint32_t[]){addr_nop, vldbc_32},
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
// VLDBC 8/16/32 bit (with address post-update)
|
||||
{
|
||||
.name = "ee.vldbc.8.ip",
|
||||
.translate = translate_vldbc_s3,
|
||||
@@ -5823,6 +6122,73 @@ static const XtensaOpcodeOps tie_ops[] = {
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
// st.qacc_x.h.32.ip / st.qacc_x.l.128.ip
|
||||
{
|
||||
.name = "ee.st.qacc_h.h.32.ip",
|
||||
.translate = translate_st_qacc_x_h_32_ip_s3,
|
||||
.par = (const uint32_t[]){wrur_qacc_h_0},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.st.qacc_l.h.32.ip",
|
||||
.translate = translate_st_qacc_x_h_32_ip_s3,
|
||||
.par = (const uint32_t[]){wrur_qacc_l_0},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.st.qacc_h.l.128.ip",
|
||||
.translate = translate_st_qacc_x_l_128_ip_s3,
|
||||
.par = (const uint32_t[]){wrur_qacc_h_0},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.st.qacc_l.l.128.ip",
|
||||
.translate = translate_st_qacc_x_l_128_ip_s3,
|
||||
.par = (const uint32_t[]){wrur_qacc_l_0},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
// ee.st.accx.ip
|
||||
{
|
||||
.name = "ee.st.accx.ip",
|
||||
.translate = translate_st_accx_ip_s3,
|
||||
.par = (const uint32_t[]){},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
// ee.ld.ua_state.ip / ee.st.ua_state.ip
|
||||
{
|
||||
.name = "ee.ld.ua_state.ip",
|
||||
.translate = translate_ld_ua_state_ip_s3,
|
||||
.par = (const uint32_t[]){},
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.st.ua_state.ip",
|
||||
.translate = translate_st_ua_state_ip_s3,
|
||||
.par = (const uint32_t[]){},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
// ee.ldxq.32 / ee.stxq.32
|
||||
{
|
||||
.name = "ee.ldxq.32",
|
||||
.translate = translate_ldxq_32_s3,
|
||||
.par = (const uint32_t[]){},
|
||||
.op_flags = XTENSA_OP_LOAD,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
{
|
||||
.name = "ee.stxq.32",
|
||||
.translate = translate_stxq_32_s3,
|
||||
.par = (const uint32_t[]){},
|
||||
.op_flags = XTENSA_OP_STORE,
|
||||
.coprocessor = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
const XtensaOpcodeTranslators xtensa_tie_opcodes = {
|
||||
|
||||
Reference in New Issue
Block a user