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16894 Commits

Author SHA1 Message Date
evan 09616c2093 fix(esp32c3): emulate GPIO interrupts 2026-07-26 15:34:45 -04:00
evan d613b079ef feat(xteink): count guest ADC reads per channel 
Host tooling needs to know when the guest has actually sampled a button,
since the firmware only polls the resistor ladder between e-ink refreshes.
 2026-07-26 11:18:28 -04:00
evan 5721bd8102 feat(xteink): wire USB serial JTAG interrupts 
Report SOF and serial-in-empty as always pending and route the peripheral
IRQ through the interrupt matrix so the ESP-IDF console driver progresses.
Merge emulator stdout into serial.log so crash output lands in one place.
 2026-07-26 09:21:43 -04:00
evan fe35cb68d6 feat(xteink): add ESP32-C3 Wi-Fi emulation with qemu AP 
Ports the ESP32 Wi-Fi emulation (esp32c3_wifi, esp32_wifi_ap, esp32_wlan_*)
from the lcgamboa/PICSimLab QEMU fork and integrates it behind the
esp32c3_wifi NIC model, plus the supporting radio peripherals
(ANA/PHYA/FE/PWR manager).

- Exposes an open SSID 'qemu' bridged to the host via QEMU user-mode NAT
  (libslirp, now enabled in the native build).
- Adds ESP-IDF 5.5 compatibility fixes: channel resolution from the
  beacon DS Parameter Set IE / AP lookup, persistent SYSCON register
  backing (phy_module_has_clock_bits), DMA inlink/outlink descriptor
  mirroring, RX descriptor ring reset on item.next==0, and descriptor
  ownership/length semantics.
- xteink-emu now starts with -nic user,model=esp32c3_wifi and synthesizes
  an eFuse image with a fixed guest MAC.

Verified against a stock Arduino-ESP32 sketch: scans, finds 'qemu',
associates, gets DHCP 192.168.4.15, and completes an outbound TCP
connection. Unmodified CrossPoint firmware still needs the power-button
hold during boot (tracked separately).
 2026-07-24 16:21:12 -04:00
evan cbeba3fbe9 fix(display): classify X3 grayscale from loaded LUTs 2026-07-21 11:42:04 -04:00
evan b0bce6c486 Add xteink browser bridge 2026-07-20 00:20:51 -04:00
evan c4227568de Add xteink machine for wasm build 2026-07-19 21:56:40 -04:00
Kohei Tokunaga e712868ec5 Update wasm backend 
Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com>
 2026-07-19 21:08:45 -04:00
Kohei Tokunaga 2816a551ef TCG: add wasm backend 
Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com>
 2026-07-19 21:08:45 -04:00
Omar Chebib 40edccac41 hw/riscv: fix interrupts being lost or delayed when MIE=0 on the ESP32-C3 2026-04-17 10:15:24 +08:00
Omar Chebib 30f83141bb hw/misc: implement SPI data transfers for the PSRAM in both QPI and OPI. 2025-08-15 09:41:13 +08:00
Yuan Yu dcf57b8d44 hw/xtensa: add CAN peripheral to ESP32 2025-07-31 14:36:30 +08:00
Omar Chebib c46f68cfd3 hw/timer: modify the ESP32-C3 TimerGroup driver to override the new generic one 2025-06-24 14:55:53 +08:00
Omar Chebib 2b7742774a hw/timer: implement an ESP32-S3 TimerGroup that overrides the new generic one 2025-06-24 14:55:53 +08:00
Omar Chebib 57330b48e4 hw/timer: implement a generic TimerGoup controller for newer Espressif targets 2025-06-24 14:55:53 +08:00
Omar Chebib 16a219aac8 misc/ssi_psram: refactor PSRAM to use a state machine 
The emulated PSRAM now internally uses a state machine, making is more sturdy
and resilient to dummy cycles.

* Fixes #57
 2025-04-03 11:56:10 +08:00
Omar Chebib ccdda32084 hw/timer: fix reset/default value for register SYSTIMER_CONF on ESP targets 
* Fixes https://github.com/espressif/qemu/issues/120
 2025-03-10 18:06:28 +08:00
Dmitry Yakovlev 7591824ec4 hw/xtensa: implement ESP32-S3 machine 
This also includes the ESP32-S3 BIOS (ROM bootloader)
 2025-02-28 16:39:03 +01:00
Dmitry Yakovlev 0c1bf393dc hw/misc: implement ESP32-S3 XTS-AES peripheral 
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
 2025-02-28 16:39:03 +01:00
Dmitry Yakovlev bd9cb721a3 hw/misc: implement ESP32-S3 Digital Signature 
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
 2025-02-28 16:39:03 +01:00
Dmitry Yakovlev e67f694323 hw/misc: implement ESP32-S3 RSA 
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
 2025-02-28 16:39:03 +01:00
harshal.patil 3629646ec5 hw/misc: Implement ESP32-S3 AES 2025-02-28 16:39:03 +01:00
harshal.patil 24deaa4323 hw/misc: Implement ESP32-S3 HMAC 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev 6c66f8c15a hw/misc: Add dummy ESP32-S3 PMS module 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev 8ab216a956 hw/nvram: Implement ESP32-S3 eFuse 
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev 015a0fbc4f hw/misc: implement ESP32-S3 RNG 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev c5a5b13d57 hw/misc: implement ESP32-S3 real-time clock module 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev 6eceeee95b hw/misc: Implement ESP32-S3 SHA 
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev 9a33d7d456 hw/dma: implement ESP32-S3 GDMA 
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
 2025-02-28 16:39:02 +01:00
Omar Chebib 81f8593bc5 hw/misc: Implement ESP32-S3 Cache (SPI Flash) 
Co-authored-by: Dmitry Yakovlev <dmitry@espressif.com>
 2025-02-28 16:39:02 +01:00
Dmitry Yakovlev e013d77398 hw/xtensa: implement ESP32-S3 Interrupt Matrix 
All features are implemented, except level/edge trigger option.
 2025-02-26 07:41:42 +01:00
Dmitry Yakovlev e458bfa43f hw/xtensa: implement ESP32-S3 clock and system registers 2025-02-26 07:41:42 +01:00
Dmitry Yakovlev 4b9285f1de hw/ssi: implement ESP32-S3 SPI1 (SPI flash) 
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
 2025-02-26 07:41:42 +01:00
Dmitry Yakovlev 79eb790ebe hw/timer: implement ESP32-S3 System Timer 
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
 2025-02-26 07:41:42 +01:00
Dmitry Yakovlev d585712419 hw/gpio: implement ESP32-S3 GPIO 
S3 GPIO overrides ESP32 GPIO driver and modifies the boot strap pin
 2025-02-26 07:41:42 +01:00
Dmitry Yakovlev dced9356d8 hw/char: implement ESP32-S3 UART 
S3 UART overrides ESP32's UART
 2025-02-26 07:41:42 +01:00
Dmitry Yakovlev 58bdf76da0 tcg: add support for 8-argument helpers 2025-02-26 07:41:41 +01:00
Omar Chebib 6353353d25 hw/riscv: implement ESP32-C3 machine 
This also includes the C3 BIOS (ROM bootloader)
 2025-02-26 07:41:41 +01:00
harshal.patil 7199aeb023 hw/misc: implement ESP32-C3 XTS-AES peripheral 2025-02-26 07:41:41 +01:00
harshal.patil 9f1a4bbec8 hw/misc: implement ESP32-C3 Digital Signature 2025-02-26 07:41:41 +01:00
harshal.patil 4479e366fb hw/misc: Implement a generic Digital Signature driver for newer Espressif targets 2025-02-26 07:41:41 +01:00
Omar Chebib e1bfe6adfd hw/misc: implement ESP32-C3 RSA 
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
 2025-02-26 07:41:41 +01:00
harshal.patil cbd9c20425 hw/misc: implement a generic RSA driver for newer Espressif targets 2025-02-26 07:41:41 +01:00
Omar Chebib 9385e8de91 hw/misc: implement ESP32-C3 AES 
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
 2025-02-26 07:41:41 +01:00
harshal.patil 78702e57a0 hw/misc: Implement a generic AES driver for newer Espressif targets 2025-02-26 07:41:40 +01:00
harshal.patil f7ade96f03 hw/misc: implement ESP32-C3 HMAC 
Added an internal HMAC implementation using the existing internal SHA APIs
 2025-02-26 07:41:40 +01:00
harshal.patil e23b18cfc2 hw/misc: Implement a generic HMAC driver for newer Espressif targets 2025-02-26 07:41:40 +01:00
Omar Chebib 95dbb0580d hw/nvram: implement ESP32-C3 eFuses 2025-02-26 07:41:40 +01:00
Omar Chebib 37f6a5ad70 hw/nvram: implement two Efuse classes for the ESP32-C3 and the ESP32-S3 
The new efuses classes are derived from the common efuse implementation: ESPEfuseClass.
 2025-02-26 07:41:40 +01:00
Omar Chebib 03ce2cfee8 hw/misc: implement ESP32-C3 RTC CNTL registers 2025-02-26 07:41:40 +01:00