24deaa4323
hw/misc: Implement ESP32-S3 HMAC
2025-02-28 16:39:02 +01:00
6c66f8c15a
hw/misc: Add dummy ESP32-S3 PMS module
2025-02-28 16:39:02 +01:00
8ab216a956
hw/nvram: Implement ESP32-S3 eFuse
...
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
2025-02-28 16:39:02 +01:00
015a0fbc4f
hw/misc: implement ESP32-S3 RNG
2025-02-28 16:39:02 +01:00
c5a5b13d57
hw/misc: implement ESP32-S3 real-time clock module
2025-02-28 16:39:02 +01:00
f59cf20d7f
hw/misc: add ESP32-S3 USB Serial JTAG as a stub
...
ESP32-C3 implementation is used.
2025-02-28 16:39:02 +01:00
6eceeee95b
hw/misc: Implement ESP32-S3 SHA
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-28 16:39:02 +01:00
9a33d7d456
hw/dma: implement ESP32-S3 GDMA
...
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
2025-02-28 16:39:02 +01:00
81f8593bc5
hw/misc: Implement ESP32-S3 Cache (SPI Flash)
...
Co-authored-by: Dmitry Yakovlev <dmitry@espressif.com >
2025-02-28 16:39:02 +01:00
e013d77398
hw/xtensa: implement ESP32-S3 Interrupt Matrix
...
All features are implemented, except level/edge trigger option.
2025-02-26 07:41:42 +01:00
e458bfa43f
hw/xtensa: implement ESP32-S3 clock and system registers
2025-02-26 07:41:42 +01:00
4b9285f1de
hw/ssi: implement ESP32-S3 SPI1 (SPI flash)
...
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
2025-02-26 07:41:42 +01:00
79eb790ebe
hw/timer: implement ESP32-S3 System Timer
...
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
2025-02-26 07:41:42 +01:00
c3a794405a
hw/timer: implement ESP32-S3 Timer Group
...
Currently ESP32-C3 implementation is used.
2025-02-26 07:41:42 +01:00
d585712419
hw/gpio: implement ESP32-S3 GPIO
...
S3 GPIO overrides ESP32 GPIO driver and modifies the boot strap pin
2025-02-26 07:41:42 +01:00
dced9356d8
hw/char: implement ESP32-S3 UART
...
S3 UART overrides ESP32's UART
2025-02-26 07:41:42 +01:00
76f9e1f154
hw/xtensa: implement ESP32-S3 TIE instructions
2025-02-26 07:41:42 +01:00
27d3ad1531
hw/xtensa: add ESP32-S3 core configuration
2025-02-26 07:41:42 +01:00
dba9c9dfa3
hw/xtensa: prepare Xtensa CPU type for extension
2025-02-26 07:41:41 +01:00
58bdf76da0
tcg: add support for 8-argument helpers
2025-02-26 07:41:41 +01:00
6353353d25
hw/riscv: implement ESP32-C3 machine
...
This also includes the C3 BIOS (ROM bootloader)
2025-02-26 07:41:41 +01:00
e9954ed253
crypto: build xts.c unconditionally
2025-02-26 07:41:41 +01:00
7199aeb023
hw/misc: implement ESP32-C3 XTS-AES peripheral
2025-02-26 07:41:41 +01:00
9f1a4bbec8
hw/misc: implement ESP32-C3 Digital Signature
2025-02-26 07:41:41 +01:00
4479e366fb
hw/misc: Implement a generic Digital Signature driver for newer Espressif targets
2025-02-26 07:41:41 +01:00
e1bfe6adfd
hw/misc: implement ESP32-C3 RSA
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:41 +01:00
cbd9c20425
hw/misc: implement a generic RSA driver for newer Espressif targets
2025-02-26 07:41:41 +01:00
9385e8de91
hw/misc: implement ESP32-C3 AES
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:41 +01:00
78702e57a0
hw/misc: Implement a generic AES driver for newer Espressif targets
2025-02-26 07:41:40 +01:00
f7ade96f03
hw/misc: implement ESP32-C3 HMAC
...
Added an internal HMAC implementation using the existing internal SHA APIs
2025-02-26 07:41:40 +01:00
e23b18cfc2
hw/misc: Implement a generic HMAC driver for newer Espressif targets
2025-02-26 07:41:40 +01:00
95dbb0580d
hw/nvram: implement ESP32-C3 eFuses
2025-02-26 07:41:40 +01:00
37f6a5ad70
hw/nvram: implement two Efuse classes for the ESP32-C3 and the ESP32-S3
...
The new efuses classes are derived from the common efuse implementation: ESPEfuseClass.
2025-02-26 07:41:40 +01:00
03ce2cfee8
hw/misc: implement ESP32-C3 RTC CNTL registers
2025-02-26 07:41:40 +01:00
e9cb83a49f
hw/misc: implement ESP32-C3 USB Serial JTAG as a stub
...
The module doesn't do much at the moment, it is used as a stub
2025-02-26 07:41:40 +01:00
6569a0882a
hw/misc: Implement ESP32-C3 SHA
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:40 +01:00
24970c0d2c
hw/misc: Implement a generic SHA driver for newer Espressif targets
2025-02-26 07:41:40 +01:00
3418debeda
hw/dma: implement ESP32-C3 GDMA
2025-02-26 07:41:39 +01:00
b4083f0cfb
hw/dma: implement a generic GDMA controller for newer Espressif targets
2025-02-26 07:41:39 +01:00
468cf78a96
hw/misc: Implement ESP32-C3 Cache (SPI Flash)
2025-02-26 07:41:39 +01:00
350ee8c75b
hw/riscv: implement ESP32-C3 Interrupt Matrix
...
All features are implemented, except level/edge trigger option.
2025-02-26 07:41:39 +01:00
373b7f8794
hw/riscv: implement ESP32-C3 clock and system registers
2025-02-26 07:41:39 +01:00
13a20b76ec
hw/ssi: implement ESP32-C3 SPI1 (SPI flash)
2025-02-26 07:41:39 +01:00
5b2eee22c5
hw/timer: implement ESP32-C3 System Timer
...
Systimer Timer is fully implemented
2025-02-26 07:41:39 +01:00
c25210517b
hw/timer: implemented a common SysTimer for the new Espressif chips
...
This new SysTiemr can be used by the ESP32-S3 and newer targets.
2025-02-26 07:41:39 +01:00
c02d3e0f4c
hw/timer: implement ESP32-C3 Timer Groups
...
All the features are supported
2025-02-26 07:41:39 +01:00
26dc5b4b85
hw/gpio: implement ESP32-C3 GPIO
...
C3 GPIO overrides ESP32 GPIO driver and modifies the boot strap pin
2025-02-26 07:41:39 +01:00
cc79a2fb98
hw/char: implement ESP32-C3 UART
...
C3 UART overrides ESP32's UART
2025-02-26 07:41:38 +01:00
85af55eeea
target/riscv: implement Espressif RISC-V CPU type
...
Espressif RISC-V CPU has a different has way of treating interrupts, which is
not standard. Thus, this class will override the default RISC-V CPU behavior
to have 31 interrupt lines.
2025-02-26 07:41:38 +01:00
c592afedea
hw/xtensa: add ESP32 machine
2025-02-26 07:41:38 +01:00
harshal.patil
Dmitry Yakovlev
Omar Chebib
Ivan Grokhotkov