 159336 at Massey
|
33cc9a8740
|
Fix gdma not checking ownership and clearing the owner bit correctly.
This didn't matter in the past but recent version of the idf check that the bit has been cleared in gdma_link_mount_buffers()
|
2026-02-03 13:53:43 +08:00 |
|
 Throows
|
ab1bfa960a
|
hw/xtensa/esp32s3: add sdmmc peripheral
|
2025-09-13 18:16:56 +02:00 |
|
 Yuan Yu
|
18a7345ed4
|
hw/net/can: remove interrupt handling from ESP32 TWAI state
|
2025-08-27 14:55:14 +08:00 |
|
 Ivan Grokhotkov
|
4f4148e2f6
|
ci: fix paths in the checksum file
|
2025-08-15 12:39:25 +02:00 |
|
 Sv. Lockal
|
2204e2b15b
|
mkvenv: Support pip 25.2
Fix compilation with pip-25.2 due to missing distlib.version
Bug: https://gitlab.com/qemu-project/qemu/-/issues/3062
Signed-off-by: Sv. Lockal <lockalsash@gmail.com>
[Edits: Type "safety" whackamole --js]
Signed-off-by: John Snow <jsnow@redhat.com>
Message-ID: <20250811190159.237321-1-jsnow@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
|
2025-08-15 11:38:40 +02:00 |
|
 Omar Chebib
|
30f83141bb
|
hw/misc: implement SPI data transfers for the PSRAM in both QPI and OPI.
|
2025-08-15 09:41:13 +08:00 |
|
|
Yuan Yu
|
8066b0c9d4
|
hw/net/can: fix CAN bus connection logic in esp32_twai.c to make sure to check if canbus is valid before connecting
|
2025-08-14 12:10:41 +08:00 |
|
|
Yuan Yu
|
38f153e737
|
hw/riscv/esp32s3: added the TWAI peripheral to the ESP32-S3 machine state and updated the machine initialization function to realize and connect the TWAI device
|
2025-07-31 14:42:57 +08:00 |
|
|
Yuan Yu
|
d5db88447b
|
hw/net/can: add ESP32-S3 TWAI peripheral emulation, which
inherits from the ESP32 TWAI implementation.
|
2025-07-31 14:42:57 +08:00 |
|
|
Yuan Yu
|
b5b69aea8a
|
hw/riscv/esp32c3: added the TWAI peripheral to the ESP32-C3 machine state and updated the machine initialization function to realize and connect the TWAI device
|
2025-07-31 14:42:57 +08:00 |
|
|
Yuan Yu
|
6e13d72071
|
hw/net/can: add ESP32-C3 TWAI peripheral emulation
Add emulation support for the ESP32-C3 TWAI (CAN bus) peripheral, which
inherits from the ESP32 TWAI implementation.
|
2025-07-31 14:42:57 +08:00 |
|
|
Yuan Yu
|
dcf57b8d44
|
hw/xtensa: add CAN peripheral to ESP32
|
2025-07-31 14:36:30 +08:00 |
|
|
Yuan Yu
|
f12f35d56e
|
hw/net/can: add emulation of SJA1000-based CAN controller for ESP32 series of chips
|
2025-07-31 14:36:30 +08:00 |
|
|
Omar Chebib
|
c46f68cfd3
|
hw/timer: modify the ESP32-C3 TimerGroup driver to override the new generic one
|
2025-06-24 14:55:53 +08:00 |
|
|
Omar Chebib
|
2b7742774a
|
hw/timer: implement an ESP32-S3 TimerGroup that overrides the new generic one
|
2025-06-24 14:55:53 +08:00 |
|
|
Omar Chebib
|
57330b48e4
|
hw/timer: implement a generic TimerGoup controller for newer Espressif targets
|
2025-06-24 14:55:53 +08:00 |
|
|
Omar Chebib
|
248b410174
|
hw/misc: optimize flash decryption speed on the ESP32
|
2025-05-13 17:30:32 +08:00 |
|
|
Omar Chebib
|
1ede4bd3d9
|
riscv: fix a bug in ESP CPU that resulted in some interrupts being dismissed
|
2025-04-17 10:02:17 +08:00 |
|
|
Omar Chebib
|
fd97b40f5a
|
hw/timer: fix several bug related to timings, both in cycle count and TimerGroup for the ESP32-C3
|
2025-04-17 10:02:17 +08:00 |
|
|
Omar Chebib
|
16a219aac8
|
misc/ssi_psram: refactor PSRAM to use a state machine
The emulated PSRAM now internally uses a state machine, making is more sturdy
and resilient to dummy cycles.
* Fixes #57
|
2025-04-03 11:56:10 +08:00 |
|
|
Omar Chebib
|
9607e26254
|
esp32: refactor drivers to use three-stage reset instead of legacy reset
|
2025-03-25 17:42:45 +08:00 |
|
|
Omar Chebib
|
e0bfd3961f
|
esp32s3: refactor drivers to use three-stage reset instead of legacy reset
|
2025-03-25 17:24:12 +08:00 |
|
|
Omar Chebib
|
95c74f43e2
|
esp: refactor Espressif generic drivers to use three-stage reset instead of legacy reset
|
2025-03-25 16:41:56 +08:00 |
|
|
Omar Chebib
|
17207a3c3f
|
esp32c3: refactor drivers to use three-stage reset instead of legacy reset
|
2025-03-25 15:36:04 +08:00 |
|
|
Omar Chebib
|
ccdda32084
|
hw/timer: fix reset/default value for register SYSTIMER_CONF on ESP targets
* Fixes https://github.com/espressif/qemu/issues/120
|
2025-03-10 18:06:28 +08:00 |
|
 Dmitry Yakovlev
|
7591824ec4
|
hw/xtensa: implement ESP32-S3 machine
This also includes the ESP32-S3 BIOS (ROM bootloader)
|
2025-02-28 16:39:03 +01:00 |
|
|
Dmitry Yakovlev
|
c0cce1fc74
|
hw/i2c: add I2C to ESP32-S3
ESP32 implementation is used as a stub.
|
2025-02-28 16:39:03 +01:00 |
|
|
Dmitry Yakovlev
|
0c1bf393dc
|
hw/misc: implement ESP32-S3 XTS-AES peripheral
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
|
2025-02-28 16:39:03 +01:00 |
|
|
Dmitry Yakovlev
|
bd9cb721a3
|
hw/misc: implement ESP32-S3 Digital Signature
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
|
2025-02-28 16:39:03 +01:00 |
|
|
Dmitry Yakovlev
|
e67f694323
|
hw/misc: implement ESP32-S3 RSA
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
|
2025-02-28 16:39:03 +01:00 |
|
 harshal.patil
|
3629646ec5
|
hw/misc: Implement ESP32-S3 AES
|
2025-02-28 16:39:03 +01:00 |
|
|
harshal.patil
|
24deaa4323
|
hw/misc: Implement ESP32-S3 HMAC
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
6c66f8c15a
|
hw/misc: Add dummy ESP32-S3 PMS module
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
8ab216a956
|
hw/nvram: Implement ESP32-S3 eFuse
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
015a0fbc4f
|
hw/misc: implement ESP32-S3 RNG
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
c5a5b13d57
|
hw/misc: implement ESP32-S3 real-time clock module
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
f59cf20d7f
|
hw/misc: add ESP32-S3 USB Serial JTAG as a stub
ESP32-C3 implementation is used.
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
6eceeee95b
|
hw/misc: Implement ESP32-S3 SHA
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
9a33d7d456
|
hw/dma: implement ESP32-S3 GDMA
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
|
2025-02-28 16:39:02 +01:00 |
|
|
Omar Chebib
|
81f8593bc5
|
hw/misc: Implement ESP32-S3 Cache (SPI Flash)
Co-authored-by: Dmitry Yakovlev <dmitry@espressif.com>
|
2025-02-28 16:39:02 +01:00 |
|
|
Dmitry Yakovlev
|
e013d77398
|
hw/xtensa: implement ESP32-S3 Interrupt Matrix
All features are implemented, except level/edge trigger option.
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
e458bfa43f
|
hw/xtensa: implement ESP32-S3 clock and system registers
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
4b9285f1de
|
hw/ssi: implement ESP32-S3 SPI1 (SPI flash)
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
79eb790ebe
|
hw/timer: implement ESP32-S3 System Timer
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
c3a794405a
|
hw/timer: implement ESP32-S3 Timer Group
Currently ESP32-C3 implementation is used.
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
d585712419
|
hw/gpio: implement ESP32-S3 GPIO
S3 GPIO overrides ESP32 GPIO driver and modifies the boot strap pin
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
dced9356d8
|
hw/char: implement ESP32-S3 UART
S3 UART overrides ESP32's UART
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
76f9e1f154
|
hw/xtensa: implement ESP32-S3 TIE instructions
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
27d3ad1531
|
hw/xtensa: add ESP32-S3 core configuration
|
2025-02-26 07:41:42 +01:00 |
|
|
Dmitry Yakovlev
|
dba9c9dfa3
|
hw/xtensa: prepare Xtensa CPU type for extension
|
2025-02-26 07:41:41 +01:00 |
|