Commit Graph

16858 Commits

Author SHA1 Message Date
Dmitry Yakovlev 58bdf76da0 tcg: add support for 8-argument helpers 2025-02-26 07:41:41 +01:00
Omar Chebib 6353353d25 hw/riscv: implement ESP32-C3 machine
This also includes the C3 BIOS (ROM bootloader)
2025-02-26 07:41:41 +01:00
harshal.patil 7199aeb023 hw/misc: implement ESP32-C3 XTS-AES peripheral 2025-02-26 07:41:41 +01:00
harshal.patil 9f1a4bbec8 hw/misc: implement ESP32-C3 Digital Signature 2025-02-26 07:41:41 +01:00
harshal.patil 4479e366fb hw/misc: Implement a generic Digital Signature driver for newer Espressif targets 2025-02-26 07:41:41 +01:00
Omar Chebib e1bfe6adfd hw/misc: implement ESP32-C3 RSA
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
2025-02-26 07:41:41 +01:00
harshal.patil cbd9c20425 hw/misc: implement a generic RSA driver for newer Espressif targets 2025-02-26 07:41:41 +01:00
Omar Chebib 9385e8de91 hw/misc: implement ESP32-C3 AES
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
2025-02-26 07:41:41 +01:00
harshal.patil 78702e57a0 hw/misc: Implement a generic AES driver for newer Espressif targets 2025-02-26 07:41:40 +01:00
harshal.patil f7ade96f03 hw/misc: implement ESP32-C3 HMAC
Added an internal HMAC implementation using the existing internal SHA APIs
2025-02-26 07:41:40 +01:00
harshal.patil e23b18cfc2 hw/misc: Implement a generic HMAC driver for newer Espressif targets 2025-02-26 07:41:40 +01:00
Omar Chebib 95dbb0580d hw/nvram: implement ESP32-C3 eFuses 2025-02-26 07:41:40 +01:00
Omar Chebib 37f6a5ad70 hw/nvram: implement two Efuse classes for the ESP32-C3 and the ESP32-S3
The new efuses classes are derived from the common efuse implementation: ESPEfuseClass.
2025-02-26 07:41:40 +01:00
Omar Chebib 03ce2cfee8 hw/misc: implement ESP32-C3 RTC CNTL registers 2025-02-26 07:41:40 +01:00
Omar Chebib e9cb83a49f hw/misc: implement ESP32-C3 USB Serial JTAG as a stub
The module doesn't do much at the moment, it is used as a stub
2025-02-26 07:41:40 +01:00
Omar Chebib 6569a0882a hw/misc: Implement ESP32-C3 SHA
Co-authored-by: Harshal Patil <harshal.patil@espressif.com>
2025-02-26 07:41:40 +01:00
harshal.patil 24970c0d2c hw/misc: Implement a generic SHA driver for newer Espressif targets 2025-02-26 07:41:40 +01:00
Omar Chebib 3418debeda hw/dma: implement ESP32-C3 GDMA 2025-02-26 07:41:39 +01:00
Omar Chebib b4083f0cfb hw/dma: implement a generic GDMA controller for newer Espressif targets 2025-02-26 07:41:39 +01:00
Omar Chebib 468cf78a96 hw/misc: Implement ESP32-C3 Cache (SPI Flash) 2025-02-26 07:41:39 +01:00
Omar Chebib 350ee8c75b hw/riscv: implement ESP32-C3 Interrupt Matrix
All features are implemented, except level/edge trigger option.
2025-02-26 07:41:39 +01:00
Omar Chebib 373b7f8794 hw/riscv: implement ESP32-C3 clock and system registers 2025-02-26 07:41:39 +01:00
Omar Chebib 13a20b76ec hw/ssi: implement ESP32-C3 SPI1 (SPI flash) 2025-02-26 07:41:39 +01:00
Omar Chebib 5b2eee22c5 hw/timer: implement ESP32-C3 System Timer
Systimer Timer is fully implemented
2025-02-26 07:41:39 +01:00
Omar Chebib c25210517b hw/timer: implemented a common SysTimer for the new Espressif chips
This new SysTiemr can be used by the ESP32-S3 and newer targets.
2025-02-26 07:41:39 +01:00
Omar Chebib c02d3e0f4c hw/timer: implement ESP32-C3 Timer Groups
All the features are supported
2025-02-26 07:41:39 +01:00
Omar Chebib 26dc5b4b85 hw/gpio: implement ESP32-C3 GPIO
C3 GPIO overrides ESP32 GPIO driver and modifies the boot strap pin
2025-02-26 07:41:39 +01:00
Omar Chebib cc79a2fb98 hw/char: implement ESP32-C3 UART
C3 UART overrides ESP32's UART
2025-02-26 07:41:38 +01:00
Ivan Grokhotkov c592afedea hw/xtensa: add ESP32 machine 2025-02-26 07:41:38 +01:00
Ivan Grokhotkov bb3fd2b886 hw/xtensa: add ESP32 interrupt matrix 2025-02-26 07:41:38 +01:00
Ivan Grokhotkov 4d8be52e30 hw/misc: add ESP32 register base addresses 2025-02-26 07:41:38 +01:00
Omar Chebib def343667b hw/display: Implement a virtual RGB screen for Espressif targets
The framebuffer emulated by this new component is fake in the sense that the
real targets don't have it, but this does make it possible to have a GUI
for programs that will run on the ESP32* targets.
2025-02-26 07:41:38 +01:00
Ivan Grokhotkov 62cdcabd79 hw/sd: add emulation of designware sdmmc controller 2025-02-26 07:41:38 +01:00
Ivan Grokhotkov d492838549 hw/timer: add ESP32 timers 2025-02-26 07:41:38 +01:00
Ivan Grokhotkov 219b511904 hw/misc: add PSRAM emulation
This is an SSIPeripheral instance that knows how to respond to read_id
command. It doesn't store any data. It is sufficient for the IDF
driver to decide to turn on the PSRAM cache. Actual data storage in
PSRAM is emulated by the cache module.

Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
Co-authored-by: Throows <throowsdev@gmail.com>
2025-02-26 07:41:38 +01:00
Ivan Grokhotkov cfc0ef0a52 hw/misc: add ESP32 flash encryption module 2025-02-26 07:41:37 +01:00
Maksim Naumenko c7d2d725c2 hw/misc: Add ESP32 LEDC 2025-02-26 07:41:37 +01:00
Maksim Naumenko 430416b022 hw/misc: add ESP32 AES 2025-02-26 07:41:37 +01:00
Ivan Grokhotkov 51e7d22ef5 hw/misc: add ESP32 SHA
Co-authored-by: Maksim Naumenko <maksim.naumenko@espressif.com>
2025-02-26 07:41:37 +01:00
Ivan Grokhotkov 389370d155 hw/misc: ESP32 RTC controller 2025-02-26 07:41:37 +01:00
Sachin Billore 1e64731f32 hw/misc: add ESP32 RSA 2025-02-26 07:41:37 +01:00
Ivan Grokhotkov e0b07af756 hw/misc: ESP32 RNG 2025-02-26 07:41:37 +01:00
Ivan Grokhotkov 959cd7267b hw/misc: add ESP32 DPORT peripheral, cache, cross-core interrupt 2025-02-26 07:41:37 +01:00
Peter Buchegger d31b34cdfe hw/i2c: add ESP32 I2C 2025-02-26 07:41:36 +01:00
Ivan Grokhotkov e593f6c308 hw/ssi: add ESP32 SPI 2025-02-26 07:41:36 +01:00
Ivan Grokhotkov dc7908f86d hw/nvram: add ESP32 eFuse 2025-02-26 07:41:36 +01:00
Ivan Grokhotkov 9251f5d161 hw/gpio: add ESP32 GPIO
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
2025-02-26 07:41:36 +01:00
Ivan Grokhotkov 0389585b22 hw/char: add ESP32 UART
Co-authored-by: Omar Chebib <omar.chebib@espressif.com>
2025-02-26 07:41:36 +01:00
Ivan Grokhotkov f08bf1a417 LOCAL: Revert tcg: Optimize inline dup_const for MO_64
This reverts commit 666cc794ab.
2025-02-26 07:41:35 +01:00
Maciej S. Szmigiero 2dc652961d target/i386: Reset TSCs of parked vCPUs too on VM reset
Since commit 5286c36622 ("target/i386: properly reset TSC on reset")
QEMU writes the special value of "1" to each online vCPU TSC on VM reset
to reset it.

However parked vCPUs don't get that handling and due to that their TSCs
get desynchronized when the VM gets reset.
This in turn causes KVM to turn off PVCLOCK_TSC_STABLE_BIT in its exported
PV clock.
Note that KVM has no understanding of vCPU being currently parked.

Without PVCLOCK_TSC_STABLE_BIT the sched clock is marked unstable in
the guest's kvm_sched_clock_init().
This causes a performance regressions to show in some tests.

Fix this issue by writing the special value of "1" also to TSCs of parked
vCPUs on VM reset.

Reproducing the issue:
1) Boot a VM with "-smp 2,maxcpus=3" or similar

2) device_add host-x86_64-cpu,id=vcpu,node-id=0,socket-id=0,core-id=2,thread-id=0

3) Wait a few seconds

4) device_del vcpu

5) Inside the VM run:
# echo "t" >/proc/sysrq-trigger; dmesg | grep sched_clock_stable
Observe the sched_clock_stable() value is 1.

6) Reboot the VM

7) Once the VM boots once again run inside it:
# echo "t" >/proc/sysrq-trigger; dmesg | grep sched_clock_stable
Observe the sched_clock_stable() value is now 0.

Fixes: 5286c36622 ("target/i386: properly reset TSC on reset")
Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Link: https://lore.kernel.org/r/5a605a88e9a231386dc803c60f5fed9b48108139.1734014926.git.maciej.szmigiero@oracle.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 3f2a05b31ee9ce2ddb6c75a9bc3f5e7f7af9a76f)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-12-22 11:18:15 +03:00