Dmitry Yakovlev
43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
/*
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* Copyright (c) 2019 Espressif Systems (Shanghai) Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#include "core-esp32s3/core-isa.h"
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#include "overlay_tool.h"
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#define xtensa_modules xtensa_modules_esp32s3
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#include "core-esp32s3/xtensa-modules.inc.c"
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extern const XtensaOpcodeTranslators xtensa_tie_opcodes;
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static const XtensaOpcodeTranslators* esp32s3_opcode_translators[] = {
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&xtensa_core_opcodes,
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&xtensa_fpu_opcodes,
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&xtensa_tie_opcodes,
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NULL
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};
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static XtensaConfig xtensa_core_esp32s3 __attribute__((unused)) = {
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.name = "esp32s3",
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.gdb_regmap = {
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.reg = {
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#include "core-esp32s3/gdb-config.inc.c"
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}
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},
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.isa_internal = &xtensa_modules,
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.clock_freq_khz = 40000,
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.opcode_translators = esp32s3_opcode_translators,
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DEFAULT_SECTIONS
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};
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REGISTER_CORE(xtensa_core_esp32s3)
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