?stateflush reuses the app-flash no-chain window without differential shadowing.
It shows that returning to C between TBs does not materialize CPUArchState; the
nostoretci reader-open corruption still reproduces.
?ramrace logs off-vCPU guest DRAM reads/writes/maps and TLB flushes. The
open-window crash shows zero such accesses, ruling out IO-thread guest-RAM
access during inflate as the compiled-store corruption source.
Skips removeFunction recycling of WASM table indices. nostoretci+noremove still
crashes 4/4, ruling out table-index reuse as the corruption source and leaving a
vCPU/IO-thread guest-RAM data race as the standing hypothesis.
Counts compiled-TB DONE_FLAG redispatch/resume re-entries. Three crashing
nostoretci runs showed zero such re-entries, ruling out the store
block-replay-via-redispatch path as the corruption trigger and pointing at a
guest-RAM data race with concurrent device/timer callbacks.
Add wasm_set_store_tci_hash and wasm_set_store_bisect so store compilation can
be split by pc hash (both widths) or bisected per width at runtime, no rebuild.
Used to show the compiled-store corruption is a nondeterministic race, not a
specific miscompiled TB: identity-independent, and a fixed config alternates
crash/pass across runs. Default path unchanged (blanket store-TCI).
The 32-bit-only store-TCI fallback passes reader-open when it works, but a
3-run benchmark hit an app-init watchdog once. Restore the upstream blanket
store-TCI fallback for reliability; keep ?nostoretci as the all-compiled repro.
The compiled-store corruption requires 8-bit and 32-bit store TB populations
compiled together. Interpreting either width breaks the interaction; keep only
32-bit qemu store TBs on TCI and allow the rest to compile. ?nostoretci remains
the all-compiled repro path.
Add an opt-in wasm_disable_store_tci() probe so browser tests can run compiled
stores at normal speed without the differential harness. Also let E11 request
no-chain only for TBs inside its PC window, avoiding the global no-chain
watchdog artifact while preserving valid per-window comparisons.
This keeps production store-TCI unchanged unless explicitly disabled.
Mode 2 runs compiled LIVE and authoritative so corruption accumulates across
TBs as in the real crash, with a per-TB TCI shadow (restored from pre-snapshot)
as the known-good reference. Store-TCI disabled under this mode; compares
env/pc/DRAM per eligible store TB, now including slow-path completions.
Result: 153k+ live-compiled comparisons, zero divergence, confirming inline
store codegen is correct even under live accumulation. Cannot reach the reader
corruption in-browser: 2x-execution + full-state snapshot trips the guest
interrupt watchdog and is throughput-bound. Suspects narrowed to the store
slow-path (helper/unwind) and store-width interaction.
Runs authoritative TCI first, snapshots its result, rewinds guest state,
runs the compiled TB as a disposable shadow, compares GPRs/DRAM, then
restores TCI. Opt-in via wasm_diff_enable(); normal execution unchanged.
Valid comparison required restoring all state a single TB can touch:
- full CPUNegativeOffsetState (the env-8 interrupt check sits before env)
- deep CPUTLB.f[].table / d[].fulltlb per MMU mode
- and skipping async cpu_exit() force-exit races.
Only side-effect-safe candidates compared (store TB, no general helper).
Result: 160k+ store-TB comparisons during reader-open, zero divergence.
Per-TB store codegen is exonerated; corruption is emergent across TBs.
The reader draws a crisp BW page, then a 4-level grayscale antialiasing
pass with inverted plane polarity (white = level 0 = both planes clear)
and near-empty planes. The old model replaced the whole frame with those
planes, wiping the page to an inverted muddle.
Model it as e-ink actually behaves: keep a persistent surface, detect
grayscale vs BW by DTM2's set-fraction (background is the white
majority), and in grayscale treat level 0 as no-drive (keep pixel) so
only the sparse antialiased edges repaint over the retained BW page. BW
refreshes still repaint every pixel. Reader text now renders sharp.
A TB containing a guest store is miscompiled by the wasm backend: it
corrupts a pointer that a later load faults on. It reproduces in uzlib
inflate during the reader's font prewarm (browser panics with a rejected
Load access fault); native QEMU decompresses the same static flash font
fine, confirming a wasm32 codegen bug.
Force store-containing TBs onto the TCI interpreter as the working
workaround. Perf ceiling: those TBs no longer JIT-compile. Upgrade path:
localize the miscompiled op in tcg_wasm_out_qemu_st and drop this.
ssi-sd now enters token mode as it returns the final R1 byte, so the
write-data token that immediately follows is not discarded. SPI CMD13
returns the internal sd_r1 response (upstream fix) instead of sd_r2_s,
which the adapter converts to the two-byte SPI R2 status; this stops the
repeated "Unexpected response to cmd 13" loop on guest status polls.
Drops the experimental store-TB TCI forcing and sd-watch OOB logging now
that the raw FAT32 image path is stable.
Diagnostic: routes store-containing TBs through TCI and logs out-of-bounds
guest stores to isolate the SdSpiCard corruption. Also carries the FAT32
vvfat root/cluster fixes and ssi-sd command framing. Squash/split before
upstreaming.
Replace three separate Jira sync workflows (new_issues.yml,
issue_comment.yml, new_prs.yml) with a single sync-jira.yml following
the recommended pattern from espressif/sync-jira-actions.
Changes:
- Migrate from espressif/github-actions/sync_issues_to_jira@master
to espressif/sync-jira-actions@v1
- Add missing GITHUB_TOKEN permissions (contents:read, issues:write,
pull-requests:write)
- Add workflow_dispatch trigger for manual syncing
- Add dynamic run-name for better visibility in Actions UI
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Node.js 20 is deprecated on GitHub Actions runners and will be forced
to Node.js 24 starting June 2, 2026, with Node.js 20 removed entirely
on September 16, 2026.
Update all actions to versions that support Node.js 24:
- actions/checkout: v4/master -> v6
- actions/upload-artifact: v4 -> v7
- actions/download-artifact: v4 -> v8
- softprops/action-gh-release: v1 -> v2
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
1. Missing bare ee.vldbc.{8,16,32} instructions - Added 3 opcode table entries with addr_nop and updated translate_vldbc_s3 to handle addr_nop without erroring.
2. Missing ee.st.qacc_{h,l}.{h.32,l.128}.ip store instructions - Added 4 opcode table entries, 2 translate functions, and 2 helper functions (with declarations in helper.h) to implement the QACC store operations as mirrors of the existing load counterparts.
3. ee.src.q incorrect qs1->qs0 copy - The bare ee.src.q qa, qs0, qs1 was incorrectly copying qs1→qs0 after the funnel shift. Per the TRM, only the .qup variant does this copy. Fixed by making the copy conditional on op_type == vmul_qup.
4. Add ee.st.accx.ip to store 40-bit ACCX (zero-extended to 64-bit) to memory, 8-byte aligned.
5. Add ee.ld.ua_state.ip to load 128-bit UA_STATE from memory, 16-byte aligned.
6. Add ee.st.ua_state.ip to store 128-bit UA_STATE to memory, 16-byte aligned.
7. Add ee.ldxq.32: Indexed load: compute address from Q register s16 segment, load 32-bit into Q register segment.
8. Add ee.stxq.32: Indexed store: compute address from Q register s16 segment, store 32-bit from Q register segment.
evan
xteink
Kohei Tokunaga
Omar Chebib
Ivan Grokhotkov
John Snow
harshal.patil
Nguyen Dinh Phi