e9954ed253
crypto: build xts.c unconditionally
2025-02-26 07:41:41 +01:00
7199aeb023
hw/misc: implement ESP32-C3 XTS-AES peripheral
2025-02-26 07:41:41 +01:00
9f1a4bbec8
hw/misc: implement ESP32-C3 Digital Signature
2025-02-26 07:41:41 +01:00
4479e366fb
hw/misc: Implement a generic Digital Signature driver for newer Espressif targets
2025-02-26 07:41:41 +01:00
e1bfe6adfd
hw/misc: implement ESP32-C3 RSA
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:41 +01:00
cbd9c20425
hw/misc: implement a generic RSA driver for newer Espressif targets
2025-02-26 07:41:41 +01:00
9385e8de91
hw/misc: implement ESP32-C3 AES
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:41 +01:00
78702e57a0
hw/misc: Implement a generic AES driver for newer Espressif targets
2025-02-26 07:41:40 +01:00
f7ade96f03
hw/misc: implement ESP32-C3 HMAC
...
Added an internal HMAC implementation using the existing internal SHA APIs
2025-02-26 07:41:40 +01:00
e23b18cfc2
hw/misc: Implement a generic HMAC driver for newer Espressif targets
2025-02-26 07:41:40 +01:00
95dbb0580d
hw/nvram: implement ESP32-C3 eFuses
2025-02-26 07:41:40 +01:00
37f6a5ad70
hw/nvram: implement two Efuse classes for the ESP32-C3 and the ESP32-S3
...
The new efuses classes are derived from the common efuse implementation: ESPEfuseClass.
2025-02-26 07:41:40 +01:00
03ce2cfee8
hw/misc: implement ESP32-C3 RTC CNTL registers
2025-02-26 07:41:40 +01:00
e9cb83a49f
hw/misc: implement ESP32-C3 USB Serial JTAG as a stub
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The module doesn't do much at the moment, it is used as a stub
2025-02-26 07:41:40 +01:00
6569a0882a
hw/misc: Implement ESP32-C3 SHA
...
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:40 +01:00
24970c0d2c
hw/misc: Implement a generic SHA driver for newer Espressif targets
2025-02-26 07:41:40 +01:00
3418debeda
hw/dma: implement ESP32-C3 GDMA
2025-02-26 07:41:39 +01:00
b4083f0cfb
hw/dma: implement a generic GDMA controller for newer Espressif targets
2025-02-26 07:41:39 +01:00
468cf78a96
hw/misc: Implement ESP32-C3 Cache (SPI Flash)
2025-02-26 07:41:39 +01:00
350ee8c75b
hw/riscv: implement ESP32-C3 Interrupt Matrix
...
All features are implemented, except level/edge trigger option.
2025-02-26 07:41:39 +01:00
373b7f8794
hw/riscv: implement ESP32-C3 clock and system registers
2025-02-26 07:41:39 +01:00
13a20b76ec
hw/ssi: implement ESP32-C3 SPI1 (SPI flash)
2025-02-26 07:41:39 +01:00
5b2eee22c5
hw/timer: implement ESP32-C3 System Timer
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Systimer Timer is fully implemented
2025-02-26 07:41:39 +01:00
c25210517b
hw/timer: implemented a common SysTimer for the new Espressif chips
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This new SysTiemr can be used by the ESP32-S3 and newer targets.
2025-02-26 07:41:39 +01:00
c02d3e0f4c
hw/timer: implement ESP32-C3 Timer Groups
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All the features are supported
2025-02-26 07:41:39 +01:00
26dc5b4b85
hw/gpio: implement ESP32-C3 GPIO
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C3 GPIO overrides ESP32 GPIO driver and modifies the boot strap pin
2025-02-26 07:41:39 +01:00
cc79a2fb98
hw/char: implement ESP32-C3 UART
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C3 UART overrides ESP32's UART
2025-02-26 07:41:38 +01:00
85af55eeea
target/riscv: implement Espressif RISC-V CPU type
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Espressif RISC-V CPU has a different has way of treating interrupts, which is
not standard. Thus, this class will override the default RISC-V CPU behavior
to have 31 interrupt lines.
2025-02-26 07:41:38 +01:00
c592afedea
hw/xtensa: add ESP32 machine
2025-02-26 07:41:38 +01:00
bb3fd2b886
hw/xtensa: add ESP32 interrupt matrix
2025-02-26 07:41:38 +01:00
4d8be52e30
hw/misc: add ESP32 register base addresses
2025-02-26 07:41:38 +01:00
def343667b
hw/display: Implement a virtual RGB screen for Espressif targets
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The framebuffer emulated by this new component is fake in the sense that the
real targets don't have it, but this does make it possible to have a GUI
for programs that will run on the ESP32* targets.
2025-02-26 07:41:38 +01:00
62cdcabd79
hw/sd: add emulation of designware sdmmc controller
2025-02-26 07:41:38 +01:00
d492838549
hw/timer: add ESP32 timers
2025-02-26 07:41:38 +01:00
219b511904
hw/misc: add PSRAM emulation
...
This is an SSIPeripheral instance that knows how to respond to read_id
command. It doesn't store any data. It is sufficient for the IDF
driver to decide to turn on the PSRAM cache. Actual data storage in
PSRAM is emulated by the cache module.
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
Co-authored-by: Throows <throowsdev@gmail.com >
2025-02-26 07:41:38 +01:00
cfc0ef0a52
hw/misc: add ESP32 flash encryption module
2025-02-26 07:41:37 +01:00
c7d2d725c2
hw/misc: Add ESP32 LEDC
2025-02-26 07:41:37 +01:00
430416b022
hw/misc: add ESP32 AES
2025-02-26 07:41:37 +01:00
3b3802923e
crypto: add more SHA implementations
...
Co-authored-by: Maksim Naumenko <maksim.naumenko@espressif.com >
Co-authored-by: Harshal Patil <harshal.patil@espressif.com >
2025-02-26 07:41:37 +01:00
51e7d22ef5
hw/misc: add ESP32 SHA
...
Co-authored-by: Maksim Naumenko <maksim.naumenko@espressif.com >
2025-02-26 07:41:37 +01:00
389370d155
hw/misc: ESP32 RTC controller
2025-02-26 07:41:37 +01:00
1e64731f32
hw/misc: add ESP32 RSA
2025-02-26 07:41:37 +01:00
e0b07af756
hw/misc: ESP32 RNG
2025-02-26 07:41:37 +01:00
959cd7267b
hw/misc: add ESP32 DPORT peripheral, cache, cross-core interrupt
2025-02-26 07:41:37 +01:00
d31b34cdfe
hw/i2c: add ESP32 I2C
2025-02-26 07:41:36 +01:00
e593f6c308
hw/ssi: add ESP32 SPI
2025-02-26 07:41:36 +01:00
dc7908f86d
hw/nvram: add ESP32 eFuse
2025-02-26 07:41:36 +01:00
9251f5d161
hw/gpio: add ESP32 GPIO
...
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
2025-02-26 07:41:36 +01:00
0389585b22
hw/char: add ESP32 UART
...
Co-authored-by: Omar Chebib <omar.chebib@espressif.com >
2025-02-26 07:41:36 +01:00
7e844444f8
target/xtensa: add ESP32 core configuration
2025-02-26 07:41:36 +01:00
harshal.patil
Omar Chebib
Ivan Grokhotkov
Maksim Naumenko
Sachin Billore
Peter Buchegger